跳到主要內容

臺灣博碩士論文加值系統

(44.192.48.196) 您好!臺灣時間:2024/06/23 20:48
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果 :::

詳目顯示

: 
twitterline
研究生:柯智偉
研究生(外文):Ke, Ji-Wei
論文名稱:適用於三維晶片的時脈同步電路
論文名稱(外文):Die-to-Die Wire-Independent Clock Synchronization for 3D IC
指導教授:黃錫瑜黃錫瑜引用關係
指導教授(外文):Huang, Shi-Yu
口試委員:李鎮宜周世傑洪浩喬
口試日期:2011-5-26
學位類別:碩士
校院名稱:國立清華大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2011
畢業學年度:99
語文別:英文
論文頁數:40
中文關鍵詞:三維晶片時脈同步電路
相關次數:
  • 被引用被引用:0
  • 點閱點閱:270
  • 評分評分:
  • 下載下載:15
  • 收藏至我的研究室書目清單書目收藏:0
This paper presents a novel die-to-die clock synchronization method that is independent of the inter-die wire delay. Through a 2-Phase All-Digital Delay Locked Loop (2P-ADDLL) and a Dual Locking Mechanism, this method can be used to maintain a global clock signal between two dies in a 3D-IC, and thereby enabling the synchronous 3D-IC design methodology. Unlike previous methods, ours does not need to know the delay of the inter-die clock wire.
現今製程技術不斷的進步下,有限平面內所能擺放的電晶體個數將因達到各元件所能容忍的最小尺寸而趨於飽和。三維晶片(3D IC)被認為可有效的解決此問題,透過垂直方向堆疊多個平面以增加擺放面積。這些垂直排列且互相平行的平面則是利用一種稱作穿矽孔(Through Silicon Via, TSV)的橋樑來進行彼此間的溝通。
這篇論文提出了一個新式裸晶與裸晶間( die-to-die )且以全標準元件( Fully cell base )實現的時脈校正( clock synchronization )電路與方法,參考之前的論文,我們是第一個提出這樣電路架構的作品,並且電路以標準元件所組成,因此易於轉移到其它製程上,會成為其優勢。
Abstract i
摘要 ii
致謝 iii
Content v
List of Figures vii
List of Tables ix
Chapter 1 Introduction 1
1.1 Introduction 1
1.2 Thesis Organization 3
Chapter 2 Preliminaries 4
Chapter 3 Overall Circuit Architecture 6
Chapter 4 The Operating Principle of The Dual Locking Mechanism 7
4.1 Dual Locking Mechanism 9
4.2 Inverse Locking: Phenomenon 12
4.3 Inverse Locking Reslolution 15
4.4 Modified Synchronization Scheme 17
4.5 Dynamic Tracking 20
Chapter 5 Describes the proposed sub-circuit 21
5.1 2-Phase Digital Controlled Delay Line 22
5.2 Period Detector 26
5.3 Tri-State Phase Detector 29
5.4 2-Phase ADDLL Timing DIagram 31
Chapter 6 Simulation Results 32
Chapter 7 Experimental Results 33
Chapter 8 Conclusion 38
Bibliography 39
[1] I. U. Abhulimen, A. Kamto, Y. Liu, S. L. Burkett, and L. Schaper, “Fabrication and Testing of Through-Silicon Vias Used in Three-Dimensional Integration,” Journal of Vacuum Science & Technology B, vol. 26, issue 6, pp. 1834-1840, Nov. 2008.
[2] G. K. Dehng, J. M. Hsu, C. Y. Yang, and S. I. Liu, “Clock-Deskew Buffer Using a SAR-Controlled Delay-Locked Loop,“ IEEE J. of Solid-State Circuits, vol. 35, no. 8, pp. 1128- 1136, Aug. 2000.
[3] C. Y. Yang, and S. I. Liu, “A One-Wire Approach for Skew-Compensating Clock Distribution Based on Bidirectional Technique,” IEEE J. of Solid-State Circuits, vol. 36, no. 2, pp. 266- 272, Aug. 2001.
[4] D. Sheng, C. C. Chung, and C. Yi. Lee, “An All-Digital Phase-Locked Loop with High-Resolution for SoC Applications,” Proc. of IEEE Int’l Symp. VLSI Design, Automation and Test, pp. 1- 4, May 2006.
[5] K. Shung and L. S. Kim, ”A High-Resolution Synchronous Mirror Delay Using Successive Approximation Register,” IEEE J. of Solid-State Circuits, vol. 39, no. 6, pp. 909- 918, Jun. 2004.
[6] D. Shin, C. Kim, J. Song, and H. Chae, “A 7ps Jitter 0.053 mm2 Fast Lock All-Digital DLL With a Wide Range and High Resolution DCC” IEEE J. of Solid-State Circuits, vol. 44, no. 9, pp. 2437-2451, Sept. 2009.
[7] R. J. Yang and S. I. Liu, ”A 40–550 MHz Harmonic-Free All-Digital Delay-Locked Loop Using a Variable SAR Algorithm,” IEEE J. of Solid-State Circuits, vol. 42, no. 2, pp. 361- 373, Feb. 2007.
[8] R. J. Yang and S. I. Liu, “A 2.5 GHz All-Digital Delay-Locked Loop in 0.13?慆 CMOS Technology,” IEEE J. Solid-State Circuits, vol. 42, no. 11, pp. 2338-2347, Nov. 2007.
[9] G. K. Dehng, J. W. Lin, and S. I. Liu, “A Fast-Lock Mixed-Mode DLL Using a 2-b SAR Algorithm,” IEEE J. Solid-State Circuits, vol. 36, no. 10, pp. 1464-1471, Nov. 2001.
[10] T. Olsson and P. Nilsson, “A Digitally Controlled PLL for SoC Application,” IEEE J. Solid-State Circuits, vol. 39, no. 5, pp. 751-760, Nov. 2004.
[11] C. N. Chuang and S. I. Liu, “A 0.5-5GHz Wide-Range Multiphase DLL With a Calibrated Charge Pump,” IEEE Transactions on Circuits and Systems, vol. 54, no. 11, pp. 939-943, Nov. 2007.
[12] S. R. Han and S. I. Liu, “A Single-Path Pulsewidth Control Loop With a Built-In Delay-Locked Loop,” IEEE J. Solid-State Circuits, vol. 40, no. 5, pp. 1130-1135, Nov. 2005.
[13] H. H. Chang, J. Y. Chang, C. Y. Kuo, and S. I. Liu, “A 0.7-2GHz Self-Calibrated Multiphase Delay-Locked Loop,” IEEE J. Solid-State Circuits, vol. 41, no. 5, pp. 1051-1061, May. 2006.
[14] Y. J. Wang, S. K. Kao, and S. I. Liu, “All-Digital Delay-Locked Loop/Pulsewidth-Control Loop With Adjustable Duty Cycles,” IEEE J. Solid-State Circuits, vol. 41, no. 6, pp. 1262-1274, June. 2006.
[15] H. H. Chang and S. I. Liu, “A Wide-Range and Fast-Locking All-Digital Cycle-Controlled Delay-Locked Loop,” IEEE J. Solid-State Circuits, vol. 40, no. 3, pp. 661-670, March. 2005.
[16] C. C. Chen and S. I. Liu, “An Infinite Phase Shift Delay-Locked Loop With Voltage-Controlled Sawtooth Delay Line,” IEEE J. Solid-State Circuits, vol. 43, no. 11, pp. 2413-2421, Nov. 2008.
[17] S. Sidiropoulos and M. A. Horowitz, “A Semidigital Dual Delay-Locked Loop,” IEEE J. Solid-State Circuits, vol. 32, no. 11, pp. 1683-1692, Nov. 1997.
[18] T. Ogawa and K. Taniguchi, “A 50% Duty-Cycle Correction Circuit for PLL output,” Proc. of IEEE Int’l Symp. on Circuits and Systems, vol. 4, pp. 21-24, May 2002.
[19] K. S. Song, C. H. Koo, N. K. Park, K. W. Kim, Y. J. Choi, J. H. Ahn, and B. T. Chung, “A Single-Loop DLL Using an OR-AND Duty-Cycle Correction Technique,” Proc. of IEEE Asian Solid-State Circuits Conference, pp. 245-248, Nov. 3-5, 2008.
[20] S. K. Kao and S. I. Liu, “A Wide-Range All-Digital Duty-Cycle Corrector with a Period Monitor,” Proc. of Electron Devices and Solid-State Circuits, pp.349-352, 2007.
[21] S. K. Kao and S. I. Liu, “All-Digital Fast-Locked Synchronous Duty-Cycle Corrector,” IEEE Trans. on Circuits and System II, Express Briefs, vol. 53, no. 12, pp. 1363-1367, Feb. 2006.

連結至畢業學校之論文網頁點我開啟連結
註: 此連結為研究生畢業學校所提供,不一定有電子全文可供下載,若連結有誤,請點選上方之〝勘誤回報〞功能,我們會盡快修正,謝謝!
QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top