臺灣博碩士論文加值系統

自半導體技術被廣泛的使用於積體電路製造40多年以來，摩爾定律一直是半導體製
造技術進步的指標 ─「每隔18～24個月，在同樣的晶片面積下，電晶體的數目可
以藉由微縮尺寸而加倍！」然而電晶體微縮有其物理上的限制，甚至摩爾博士本人
也在2005年公開表示摩爾定律並非毫無止境，畢竟電晶體微縮技術是不可能分割原
子。但是市場對電子產品功能的需求並無限制，在既要滿足消費者對產品的功能成
長期待但卻受限於實際的製造技術的情況下，三維晶片的製造技術重新被提出。三
維晶片的概念最早是在1958年提出，但當時由於並未感受到微縮生產的困難度，所
以並沒有被深入研究。目前，在微縮技術成本極高且極難的比較下，三維晶片技術
相對可以用另外一種方式延續摩爾定律。

三維晶片是指在薄化後的晶片內部形成為數眾多的垂直銅柱導線，這垂直導線則稱
為穿矽孔（Through-Silicon Via）；薄化後的晶片可以在垂直方向堆疊，並利用
這些穿矽孔上、下傳遞信號。簡言之，三維晶片技術就是將數個晶片薄化後，在晶
片內部打孔形成穿矽孔，再將這些晶片以穿矽孔「釘」在一起，因此三維晶片包括
（1）晶圓薄化技術，（2）穿矽孔技術及（3）晶片堆疊技術。一個三維晶片可以
是數顆晶片堆疊後的成品，因此「在同樣的晶片面積下」，電晶體的數目也可以藉
由「三維晶片技術」而增加數倍。然而目前三維晶片的製造技術尚未成熟，因此需
要藉由修補技術來提高三維晶片的良率。

在本篇論文中，我們聚焦在三維晶片的修補方法及可修補的電路設計。我們利用穿
矽孔形成可在垂直方向交換信號水平位置的硬式開關（稱為DTHS），利用這些硬式
開關來重新規劃三維晶片內電路區塊的電源及信號路徑。事實上，在單晶片或記憶
體電路設計中，根據電壓、頻率或矽智財等，晶片已經自然被分為數個電路區塊，
這些區塊間以信號彼此連接。當某個電路區塊失敗時，即便是其餘電路區塊仍可正
常工作，這顆晶片還是得被宣告為壞晶片。如果有兩顆壞晶片但他們壞掉的電路區
塊並不相同，我們可以利用三維晶片技術將兩顆壞晶片堆疊起來，並利用DTHS將壞
掉或沒用到的電路區塊的電源關閉，同時也用DTHS將兩個晶片的電路區塊連接起來
，這樣堆疊起來的三維晶片就變成好晶片。

這種三維晶片的修補方法，在功耗上與原來的系統晶片相當，在效能上則略遜一籌
，這是由於加入TSV後的信號延遲和三維晶片的散熱問題造成產品效能遞減，事實
上經由三維晶片技術修補後的產品原本就是被當成降級後的產品。本論文研究動機
是基於在產品初期良率往往不高，這些壞晶片如果能有效運用，可以減低製造成本
並幫助產品問世，因此，我們想到利用三維晶片來對這些壞晶片進行堆疊修補，增
加好晶片的數目。

此外我們也在論文中提出配對壞晶片的方法，利用這種方法可以充分使用壞晶片以
達到最高的修補成功率。最後，我們以兩個靜態隨機存取記憶晶片（SRAM）來驗證
所提出的三維晶片修補方法。量測結果顯示，修補後的晶片不管是在功耗或在速度
上都和原來的好晶片相差不遠，證實這種方法的確可以應用在實際產品上。

In view of the challenges encountered by CMOS scaling, it seems inevitable that a highly integrated system on chip (SOC) must start from low production yield, and then it takes tremendous time and effort to improve the yield to a reasonably high level. Three-dimensional (3-D) integration can provide a means to overcome the difficulties in the design and manufacturing of these SOC products. On the other hand, the yield rate is also an unsolved issue of 3-D integrated circuit (IC). To improve the yield rate of the 3-D IC, it is important to have the repair mechanism in the design. Unfortunately, so far, there is little research for 3-D IC repair. In our study, we can classify the 3-D repair into three types: (1) the redundancy is on-chip and the enabling circuit is also on the same chip; (2) the redundancy is on-chip but the enabling circuit is on another chip, and (3) the redundancy is on another chip and the enabling circuit can be on a third chip. From another perspective, introducing vertical interconnects, such as through-silicon via (TSV), makes it feasible to stack multiple bad dies, each failing some but not the same parts, to produce a good die stack. In other words, the IC can become usable in the 3-D form, by patching a bad die by other bad dies. To exercise the third type of the 3-D repair method, we focus a TSV-based repair method in this paper. We propose a method to achieve this by using a dual-TSV hardwired switch (DTHS). Each DTHS is composed of at most two TSVs and four bond pads, connected by front-side and backside redistribution layer (RDL) metal lines in an orthogonal or twisted pattern. The location to form the TSV can be programmed by a direct write process, such as laser drilling. This type of TSV has been shown to enjoy better cost-effectiveness, if its usage is limited to a certain amount, say, 250,000 per wafer. We incorporate the DTHS in the design under such a restriction and enable the built-in circuit to establish the intra-die routing. In order to be a 3-D reparable IC, the original design needs to be modified. We also propose a modification method from the system point of view. For a SOC or memory design, it may be already partitioned into several separable parts by functionalities or power domains. Each part has its individual power connections such that it can be independently turned on or off. The effort of the modification is minor, because the SOC is readily composed of modules with predefined functions and power supplies. The DTHS herein is used: (1) to shut off the power connections and (2) to disconnect signal paths from both failing and unused parts and redirect them to the functional parts among the stacked dies. The shutoff makes the 3-D repaired IC consume almost the same power and also helps to remove some failures, such as excessive leakage and interconnection shortage; the isolation completely shuns signal conflicts. Although the speed is degraded due to the extra load incurred by DTHS, our simulation in a 65nm process shows the delay time is within 350ps which may still be justifiable. The performance degradation turns out to be a necessary evil, since inherently the die stack has poorer thermal conductivity than its two-dimensional (2-D) counterpart.
Because the repair process is a post processing after the mass production, we think that 3-D repair should not influence the normal manufacture. The penalty of 3-D repair is that a new test flow is needed to sort out failing parts in the bad dies which may induce an extra testing cost. Since the manufacturing cost of the bad dies is already charged to and amortized by the good ones, the repair cost is the main concern when determining if a 3-D patched IC is worthwhile. To justify the concept of this paper, we use the SRAM test chip to do 3-D repair, and the measurement results show that 3-D repair is feasible. Even so, the 3-D repaired IC is deemed to be a transitional-period product. Nevertheless, it does help to shorten time-to-market and make the irreparable die profitable

1 Introduction
1.1 Why Repair Method for 3-D Integrated Circuit
1.2 3-D Integration Technologies
1.2.1 Front-Side Via-Last Process
1.2.2 Backside Via-Last Process
1.2.3 Via-Middle Process
1.2.4 Via-First Process
1.2.5 Summary
1.3 Organization of the Thesis
2 Hard-Wired Switch
2.1 Dual-TSV Hard-Wired Switch (DTHS)
2.1.1 Basic Structure
2.1.2 Pass-Mode (II-mode) DTHS
2.1.3 Cross-Mode (X-mode) DTHS
2.1.4 Other Available Modes of DTHS
2.2 Transformation: Twist-TSV Hard-Wired Switch (TTHS)
2.2.1 Basic Structure
2.2.2 Pass-Mode (II-Mode) TTHS
2.2.3 Cross-Mode (X-Mode) TTHS
2.2.4 Other Available Modes of TTHS
3 Design of a Reparable 3-D SOC
3.1 Floorplan Modification for 3-D Reparable SOC
3.1.1 Floorplan of The Traditional SOC Design
3.1.2 Floorplan of a Reparable SOC Design
3.2 Design Modification for 3-D Reparable SOC
3.2.1 Power Re-routing
3.2.2 Signal Re-routing
3.2.3 Isolation Circuit
3.2.4 A Case Study
3.3 Area Overhead and Performance Study
3.3.1 Area Overhead of 3-D Repaired IC
3.3.2 Performance of 3-D Repaired IC
4 Design of a Reparable 3-D Memory
4.1 Floorplan Modification for 3-D Reparable Memory
4.1.1 Floorplan of Traditional Memory Design
4.1.2 Floorplan of a 3-D Reparable Memory Design
4.2 Design Modification for 3-D Reparable Memory
4.2.1 Address/Command/Data-input Circuit
4.2.2 Data Path Circuit
4.3 Area Overhead and Performance Study
4.3.1 Area Overhead of 3-D Repaired Memory
4.3.2 Performance of 3-D Repaired Memory
5 Yield Improvement and Matching Method
5.1 Analysis of Yield Improvement
5.2 Analysis of Design Blocks
5.3 Matching Method for Bad-Die Recycling
6 Experimental Results
6.1 3-D Repaired SRAM Test Chip
6.2 Measurement Results
7 Conclusion and Future Work
7.1 Conclusion
7.2 Future Work

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