臺灣博碩士論文加值系統

隨著製程為了繼續遵循莫爾定律不斷演進，我們必須面對須多技術上的困難及物理上瓶頸，其中包含走線RC延遲、漏電流上升以及生產上的難度提升。而目前最有潛力能突破莫爾定律並有效提升效能及密度的方法就是三維製程整合。目前三維製程的開發正在萌芽階段，但有許多問題已經開始浮現，如:直通矽穿孔負載過重導致效能不彰、直通矽穿孔過大使得面積效益不佳及多層電路定址問題等。因此如何提高TSV之傳輸速度以及設計適合堆疊之架構已經成為了三維製程整合的重要議題。而為了展現三維整合的優勢，我們可以利用通用記憶體容量平台的概念來以預先設計、多層堆疊的方式來滿足不同系統的需求，如此則可以減少上市時間並同時降低成本。
因此，為了符合這種通用記憶體容量平台的特性，在論文中我們提出了自我時序追蹤差動直通矽穿孔傳輸方案，其中包含了差動小訊號方案及自我時序追蹤方案兩種方案。其中差動小訊號方案能夠有效提高直通矽穿孔下的傳輸效率，即使是在多層堆疊的情形下也能夠有效降低傳輸速度的損失。而自我時序追蹤方案則可以在不同層數堆疊的情形下精準的控制操作時序，並在直通矽穿孔負載改變情形下自動調整至適當的操作時序，也因此可以同時支援任意層數的堆疊及適應直通矽穿孔的製程變異。
一個由三萬兩千字元所組成的雙層三維靜態隨機存取記憶體陣列使用了一百八十奈米互補金氧半技術製造來驗證我們的想法，量測結果顯示在我們的架構能夠適應至少二十層的堆疊，並且在二十層堆疊時較單端傳輸降低百分之三十四點三的存取速度損失。

We have to face a lot of technical difficulties and physical limitations as process fol-lows Moore’s Law continuously. These challenges include increasing of wire RC delays, rising of leakage and manufacturing challenges. 3D integration has the most potential to solve these problems and provide outstanding performance and high density at the same time. But there are many issues surfaced such as the heavy loading of TSV, large TSV pitch and multi-layer addressing. Therefore, how to improve the transfer performance and provide efficiency circuit architectures has been an important issue. In order to demonstrate the advantages of 3D integration, we can satisfy various system requirements using pre-designed logic and different stacking number of memory with universal memory capacity concept. In the thesis, we proposed Self-Timed Differential-TSV Signal Transfer Scheme to reduce the speed penalty of TSV and support the multi-layer stacking function at the same time. On the other hand, the effect of TSV process variation can be reduced also. A 32kb 2 layer 3D-SRAM macro has been fabricated in 0.18um bulk CMOS technology to verify the idea of this work. The measurement results demonstrate that this design can support 20 layers stacking at least and reduce the access time penalty about 34.3% in 20 layers staking compare to single end transfer scheme.

摘要 i
Abstract ii
致謝 iii
Contents iv
List of Figures vii
List of Tables xi
Acronyms xii
Chapter1 Introduction 1
1.1 Motivation and Application for 3D-SRAM 1
1.2 Emerging Technology: 3D-IC 4
1.2.1 Die/Wafer Assembly 4
1.2.2 Bonding Styles 5
1.2.3 TSV Process Flow 6
1.3 Thesis Organization 9
Chapter2 Characteristic and Analysis of ITRI 3D IC Process 11
2.1 Introduction to ITRI 3D IC Process [22] 11
2.2 RC Characteristic Analysis for ITRI 3D Process 13
Chapter3 Design Challenge of 3D SRAM 16
3.1 Novel Architecture for 3D Memory Integrated Application 16
3.1.1 Conventional Direct Stacking and Master-Slave Architecture 17
3.1.2 3D Multi-Ported SRAM Arrays 20
3.1.3 3D Ultra-high Bandwidth Memory 23
3.1.4 3D System Integration Using Inductive-Coupling Link 25
3.2 Process Variation and Timing Tracking Design 27
3.2.1 Process Variation 27
3.2.2 Timing Tracking Design 28
Chapter4 Proposed Self-Timed Differential-TSV Signal Transfer Scheme 30
4.1 Concepts of Proposed STDT Scheme 30
4.2 Differential Small-Voltage-Swing Scheme 31
4.3 Self-Timed Tracking Scheme 34
4.4 Combination of DSVS and STT 37
Chapter5 Analyses and Comparisons of Proposed STDT Scheme 40
5.1 Speed Comparison of STDT & Single End 40
5.1.1 Transfer Speed Using the Same Driver Size 40
5.1.2 Access Time of Stacked SRAM Macros 42
5.2 Power Consumption and Peak Current Analysis 43
5.2.1 Power Consumptions of STDT Scheme 43
5.2.2 Peak Current Analysis for STDT Scheme 46
5.3 Area Penalty Analysis for STDT Scheme 48
Chapter6 Macro Implementation 49
6.1 Architecture of Proposed 3D-SRAM 49
6.2 Test Chip Design 53
Chapter7 Experimental Results and Conclusions 56
7.1 Measurement Results 56
7.2 Conclusion of This Thesis 61
7.3 Future work 63
References 64

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