臺灣博碩士論文加值系統

近年來因應元件微縮的需要，所以必須在閘極介電層使用高介電常數材料。經過學界及業界多年的研究，二氧化鋯（ZrO2）及二氧化鉿（HfO2）是較具有潛力的high-k材料，在研究主題上我選擇以ZrO2做為閘極介電層的材料，因為ZrO2和HfO2相較起來ZrO2較容易結晶成四方晶態（tetragonal phase），其介電常數可以高達39，藉此可以降低等效氧化層厚度，更利於元件之微縮。
第一部份實驗中我們利用ZGZ（ZrO2/Ge/ZrO2）堆疊式結構，當鍺（Ge）擴散進入ZrO2會降低ZrO2結晶成tetragonal phase所需之溫度，可在低溫500 oC下達成，經過我們的實驗發現其介電常數高達36.2，而EOT為1.75 nm，並使用氮氧化矽（SiON）作為介面層輔以氨電漿及氫氣處理，有效鈍化tetragonal-ZrO2中之缺陷（traps），改善結晶後漏電流過大的問題，使漏電流在-1 V時可降低至4.8×10-8 A/cm2，除此之外，氨電漿處理對於元件的可靠度亦能有所改善，使經過氨電漿鈍化的tetragonal-ZrO2非常適合拿來做為high-k閘極介電層。
在實驗的第二部分希望能夠在非結晶的情況下能夠使EOT有明顯的下降，因為結晶必定會有漏電流過大可靠度及穩定性變差的問題使元件的特性劣化，所以我們採用ZLZ（ZrO2/La2O3/ZrO2）堆疊式結構來形成非晶的(ZrO2)x(La2O3)1-x介電層，同樣以SiON做為介面層，由於紅外線主動橫向光學聲子軟化效應，介電常數上升使EOT大幅度的下降至1.53 nm，且在-1 V時有相當低的漏電流3.0×10-9 A/cm2，由於SiON介面層品質很好的緣故，介面缺陷密度（Dit）維持在1.52×1011 cm-2eV-1，且在可靠度的表現也相當優秀，意味著非晶態的(ZrO2)x(La2O3)1-x介電層是能應用在先進CMOS上的一種新技術。

A ZrO2/Ge/ZrO2 laminate and a subsequent annealing at 600 oC was employed to formed a Ge-stabilized tetragonal ZrO2 (t-ZrO2) dielectrics with permittivity of 36.2. On Si substrate, with thin SiON as an interfacial layer, the SiON/t-ZrO2 gate stack with equivalent oxide thickness (EOT) of 1.75 nm shows tiny amount of hysteresis and negligible frequency dispersion in capacitance-voltage (C-V) characteristics. Moreover, by employing additional NH3 nitridation to passivate the leaky channels derived from grain boundaries, the leakage current achieves 4.8×10-8 A/cm2 at Vg=Vfb-1 V and the satisfactory reliability confirmed by positive bias temperature instability (PBTI) test is also obtained.

An amorphous (ZrO2)x(La2O3)1-x alloy formed by deposition of a ZrO2/La2O3/ZrO2 laminate and a subsequent annealing was employed as the gate dielectric for metal-oxide-semiconductor (MOS) devices and the impact of a SiON interfacial layer on device performance was also explored. By integrating the (ZrO2)x(La2O3)1-x alloy and SiON interfacial layer as the gate stack, and the (ZrO2)x(La2O3)1-x alloy is found to have a high κ value of 28.2 with negligible amount of bulk traps, both of which are very desirable for advanced gate dielectrics. This gate stack displays good frequency dispersion in capacitance-voltage (C-V) characteristics which confirm the low interfacial trap density. In addition, MOS devices demonstrate leakage current of 2.1×10-7 A/cm2 at the gate voltage of -1 V with equivalent oxide thickness (EOT) of 1.53 nm and this performance is superior to other high-κ gate dielectrics.

第一章 序論 1
1-1 前言 1
1-2 研究動機 3
1-3 論文架構 5
第二章 文獻回顧 9
2-1高介電常數材料的發展 9
2-2 介電層結晶性探討 10
2-3 摻雜效應對於ZrO2結晶之探討 11
2-4 氨電漿對氧空缺之鈍化效果 12
2-5 La的氧化物做為High-k介電層之探討 13
第三章 實驗原理與流程 19
第一部分 實驗相關原理 19
3-1 MOS電容操作機制 19
第二部分 實驗設計與流程 21
3-2實驗規畫 21
3-3 TaN/Ta/ZrO2/Ge/ZrO2/SiON/Si 電容製程 22
3-4 TaN/Ta/ZrO2/La2O3/ZrO2/SiON/Si 電容製程 23
第四章 實驗結果與討論 30
第一部分tetragonal-ZrO2薄膜電性及物性分析 30
4-1 tetragonal-ZrO2薄膜物性分析 30
4-1-1 X射線繞射分析（X-ray Diffraction） 30
4-1-2 XPS（X-ray Photoelectron Spectroscopy） 31
4-2 tetragonal-ZrO2薄膜電性分析 33
4-2-1 電容電壓特性分析 33
4-2-2 磁滯及頻散現象分析 34
4-2-3 電流電壓特性分析 35
4-2-4 電流對EOT特性分析 35
4-2-5 可靠度分析 36
第二部分(ZrO2)x(La2O3)1-x薄膜電性及物性分析 37
4-3 (ZrO2)x(La2O3)1-x薄膜物性分析 37
4-3-1 X射線繞射分析（X-ray Diffraction） 37
4-3-2 XPS（X-ray Photoelectron Spectroscopy） 37
4-4 (ZrO2)x(La2O3)1-x薄膜電性分析 38
4-4-1 頻散現象分析 38
4-4-2 介面缺陷密度及磁滯現象分析 39
4-4-3電容電壓特性分析 40
4-4-4 電容電壓特性及漏電機制分析 41
4-4-5 電流對EOT特性分析 42
4-4-6 可靠度分析 42
第五章 結論 63
參考文獻 65

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