臺灣博碩士論文加值系統

由於LDO主要功能是要把高電壓(Input)降到低電壓(Output)，輸出為一個定電壓值，也可以說是個穩壓器，如果穩壓器的電壓供给IC之相關產品使用，產品輸出電壓能越穩定越好，不會因為輸入電壓變動而輸出電壓跟著變動，所以電源拒斥比在LDO固然是一項非常重要的規格，電源拒斥比越高越好，表示對電源端的雜訊抵抗能力越佳。
本架構提出使用疊接技巧，使輸出阻抗增加，使輸出電壓不易受輸入電壓變動而改變，而產生乾淨而穩定的電壓，作為晶片內部其他電路的工作電壓。
本論文以台積電0.18um 1P6M製程實現，晶片面積為0.872×0.561 mm2，晶片量測之整體電源拒斥比在60MHz時，整體的PSR維持在-37.7dB左右，功率消耗為 2.13mW，效率為77%。

The main function of the LDO circuit is to produce a low output voltage from a high-input voltage with a very low dropped out voltage. The idea is to generate a fixed output voltage like a regulator. Regulated voltage supply for IC products is required for some applications. Hence, the more stable output voltage of a regulator the better. This means, any variations at the input voltage will not affect the output voltage. To achieve this characteristic of the output voltage of the LDO, the power supply rejection ratio must be high as possible. Higher PSR means higher noise immunity thus making the output voltage to be less sensitive to any input voltage variations.
In this work, a cascade technique is used to increase the output impedance of the LDO so that the output voltage can be less susceptible to any changes in input voltage. With this technique, a clean and stable voltage can be produced.
The test chip is implemented by TSMC 0.18um 1P6M process. The chip area is 0.872×0.561 mm2, the measured PSR at full load without using large output capacitor is -37.7 dB at 60MHz and ripple is 28mV, the power consumption is 2.13 mW and the efficiency is 77%.

謝　辭 i
中文論文提要 iii
英文論文提要 iv
目　錄 v
圖目錄 vii
表目錄 x

第一章　緒　論 1
1.1　研究動機與目的 1
1.2　論文章節安排 2

第二章　穩壓器電路之先前技術 3
2.1　傳統低壓降線性穩壓器概論 3
2.2　傳統低壓降線性穩壓器之重要特性參數介紹 4


第三章　新式穩壓器電路之設計原理 18
3.1　電路架構操作 18
3.2　Two-Stage OP之設計 30
3.3　Folded-Cascode OP之設計 38
3.4　狄克森充電器電路 42
3.5　參考電流源電路 44
3.6　電路比較 46

第四章　模擬結果分析與比較 49
4.1　參考電壓源之模擬 50
4.2　Two-Stage Amplifier之模擬 51
4.3　Folded-Cascode Amplifier之模擬 53
4.4　Diskson Charge Pump之模擬 54
4.5　整體電路之模擬 55
4.6　整體電路SS、TT、FF之post-sim結果 60
4.7　電路佈局 64
4.7.1　電路佈局 64
4.8　測試規劃與晶片量測 72
4.8.1　測試規劃與晶片量測 72
4.9　晶片測試結果 75
4.9.1　量測結果 75

第五章　結論與未來方向 80
5.1　結論 80
5.2　未來方向 81

參考文獻 82


圖　目 錄 頁數
Fig 2.1 低壓降線性穩壓器的基本結構 4
Fig 2.2 在固定負載下之輸出電壓與輸出電壓特性 6
Fig 2.3 線電壓調節率 7
Fig 2.4 負載調節率 8
Fig 2.5 接地電流 9
Fig 2.6 暫態響應 10
Fig 2.7 輸出電壓誤差 11
Fig 2.8 差動誤差、電阻誤差造成之輸出準確率 12
Fig 2.9 交流等效模型 13
Fig 2.10 LDO電路化簡 15
Fig 2.11 LDO交流等效模型 15

Fig 3.1 新型低壓降線性穩壓器之架構圖 18
Fig 3.2 新型低壓降線性穩壓器之NMOS化簡圖 21
Fig 3.3 新型低壓降線性穩壓器NMOS之小訊號 21
Fig 3.4 新型低壓降線性穩壓器之PMOS化簡圖 26
Fig 3.5 　 新型低壓降線性穩壓器PMOS之小訊號 26
Fig 3.6 　 傳統與新型低壓降線性穩壓器極、零點位置比較 30
Fig 3.7 　 傳統Two-Stage Operational Amplifier架構 31
Fig 3.8 等效電路 33
Fig 3.9 頻率增益相位圖 37
Fig 3.10 Folded-Cascode Amplifier架構 38
Fig 3.11 Cascode Current Mirror架構 39
Fig 3.12 第二級之疊接技巧 41
Fig 3.13 狄克森充電器電路 43
Fig 3.14 current reference Circuit 44
Fig 3.15 啟動電路之電流曲線 45
Fig 3.16 比較新型低壓降線性穩壓器之架構圖 46
Fig 3.17 Without Bias之Load Regulation 模擬圖 47
Fig 3.18 With Bias之Load Regulation 模擬圖 48

Fig 4.1 能隙參考電路 50
Fig 4.2 輸出參考電壓 51
Fig 4.3 誤差放大器之增益以及相位響應 52
Fig 4.4 Folded Cascode OP之增益以及相位響應 53
Fig 4.5 顯示Charge Pump電壓為2.7V 55
Fig 4.6 LDO系統穩定度模擬 56
Fig 4.7 Folded Cascoded系統穩定度分析 57
Fig 4.8 Two Stage系統穩定度分析 57
Fig 4.9 顯示整體電路的PSR 58
Fig 4.10 顯示pre-sim的輸出Ripple 58
Fig 4.11 顯示Vdd從1.6V慢慢上升至2V，輸出仍然穩再1.4V 59
Fig 4.12 顯示Vdd從0V慢慢上升至1.8V，輸出仍然穩再1.4V 59
Fig 4.13 顯示post-sim的輸出Ripple 61
Fig 4.14 顯示Vdd從1.6V慢慢上升至2V，輸出仍然穩再1.4V 61
Fig 4.15 FF模擬，輸出仍維持1.4V 62
Fig 4.16 SS模擬，輸出仍維持1.4V 62
Fig 4.17 TT模擬，輸出仍維持1.4V 63
Fig 4.18 兩極差動放大器 65
Fig 4.19 折疊疊階放大器 65
Fig 4.20 參考電壓源 66
Fig 4.21 狄克森充電器 67
Fig 4.22 負載電容 68
Fig 4.23 (a)LDO之分壓電阻(b)匹配方式 68
Fig 4.24 (a)LDO之分壓電阻(b)匹配方式 68
Fig 4.25 驅動晶體 69
Fig 4.26 晶片佈局Floor Plan 70
Fig 4.27 晶片佈局全圖 70
Fig 4.28 晶片照相圖 71
Fig 4.29 量測考量之模擬環境 73
Fig 4.30 LM317整流器 73
Fig 4.31 整流器輸出端之旁路濾波器 74
Fig 4.32 量測儀器相片RS2208A 74
Fig 4.33 LDO路電路量測環境設定 74
Fig 4.34 LDO 量測電路板 76
Fig 4.35 印刷電路板佈局圖 76
Fig 4.36 穩壓器的輸出電壓與負載電流之關係 77
Fig 4.37 輸出電壓 77
Fig 4.38 Line Regulation 量測結果 78
Fig 4.39 負載電流脈衝 78
Fig 4.40 負載電流脈衝 79



表　目 錄
頁數
Table. 4.1 Corner驗證條件 49
Table. 4.2 OP規格表 52
Table. 4.3 Folded Cascode OP規格表 54
Table. 4.4 比較表 63
Table. 4.5 Pin name description of the type1 test chip 72
Table. 4.6 使用儀器表 75
Table. 4.7 穩壓器晶片量測結果 79

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