臺灣博碩士論文加值系統

100-Gb/s乙太網路為下一代乙太網路系統所推行之標準，其應用同時包含了伺服器運算與網路聚集等範圍。本篇論文提出一可應用於100-Gb/s乙太網路系統之2 × 25-Gb/s接收機，以65奈米CMOS製程所設計。雖然相對於系統所採用的四通道架構，此接收機只已雙通道方式實現，但由於不同通道間的資料傳輸處理是彼此獨立的，因此雙通道的操作方式是可完全相容於四通道的架構。此接收機主要包含了三個有線通訊接收端的關鍵元件，分別是限幅放大器、時脈與資料回復電路、解多工器。首先，兩個相同的25-Gb/s限幅放大器具有高增益以及高頻寬，使其輸出信號能有夠大的振幅以及最小的自生時脈抖動。同時我們提出一新的偏壓技術，減低因製程或溫度變化所造成之放大器增益頻寬變異。接著為兩個全速架構且低功耗之時脈資料回復電路，它採用了混波器架構之線性相位偵測器，以及自動頻率鎖定技巧。在相位偵測器中，我們藉由將時脈信號與資料轉態脈衝信號進行混波，其輸出結果會正比於相位誤差，使之可以達到高速操作的能力。在頻率探測迴路中，利用了不同相位的資料信號去獲取頻率偏差的資訊，而非利用時脈信號，並免除了外部參考時脈信號。最後，此接收器電路整合了一高速的二比五解多工器(包括了一內建之時脈產生器)。此分數比例之解多工是以一高效能之兩步驟轉換方式實現。此雙通道接收器使用1.2伏特之供應電壓，消耗功率為510毫瓦，在位元錯誤率小於10^−12的情況下，可以達到20峰對峰毫伏特之輸入敏感度。

The 100-Gb/s Ethernet (100GbE) is the next generation''s Ethernet standard, which aims at the applications of both server computing and network aggregation. In this dissertation, a 2 × 25-Gb/s receiver for 100GbE has been implemented in 65-nm CMOS technology. Although only 2 channels are implemented, this receiver provides exactly the same operation as a 4-channel one while dealing with independent channels. It is mainly composed of three critical components of a wireline receiver, limiting amplifier, clock and data recovery (CDR), and demultiplexer (DMUX). Two identical 25-Gb/s limiting amplifiers provide high-gain and broad-bandwidth to achieve a large output swing with minimum inherent jitter. A novel regulation mechanism is applied to the limiting amplifiers to minimize its gain and bandwidth variations. Two low-power full-rate CDRs employ mixer-type linear phase detectors and automatic frequency locking techniques. The phase detector achieves high-speed operation by mixing the clock with the data-transition pulses, providing output proportional to the phase error. The frequency acquisition loop utilizes the data phases rather than the clock phases to distill the frequency difference, and no external reference is used in this design. A high-speed 2:5 DMUX circuit (with a built-in clock generator) is also integrated. The fractional-ratio demultiplexing is realized by an efficient two-step conversion scheme. This two-channel receiver achieves BER < 10^−12 with 20-mVpp input sensitivity while consuming a total power of 510 mW from a 1.2-V supply.

摘要 I
Abstract III
Contents V
List of Figures VII
List of Tables XI
Chapter 1 Introduction 1
1.1 Overview of Optical Communication 1
1.2 100-Gb/s Ethernet 5
1.3 Dissertation Organization 11
Chapter 2 Receiver Architecture 13
2.1 Introduction 13
2.2 Architecture 16
Chapter 3 Limiting Amplifier 19
3.1 General Consideration 19
3.2 Proposed Architecture 20
3.3 Gain-Regulating Bias Circuit 23
3.4 Bandgap Reference 25
3.5 Conclusion 26
Chapter 4 Clock and Data Recovery Circuit 29
4.1 Introduction 29
4.2 CDR Architecture 33
4.3 Building Blocks 46
4.4 Experimental Results 55
4.5 Conclusion and Modification on the Receiver 60
Chapter 5 2:5 Demultiplexer 63
5.1 General Considerations 63
5.2 Demultiplexer Architecture 64
5.3 Clock Generator 70
Chapter 6 Experimental Results 75
Chapter 7 Conclusion 85
Bibliography 87
Publication List 93

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