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研究生:戴承雋
研究生(外文):Cheng-Jiun Dai
論文名稱:實現0.8V基體互補式金氧半動態臨限電壓技術設計低功率系統晶片應用
論文名稱(外文):Chip Realization of 0.8V Bulk CMOS DTMOS Technique for Optimization of Low-Power System Applications
指導教授:郭正邦郭正邦引用關係
口試委員:葉正信陳正雄
口試日期:2011-06-26
學位類別:碩士
校院名稱:國立臺灣大學
系所名稱:電子工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2011
畢業學年度:99
語文別:中文
論文頁數:46
中文關鍵詞:電子設計自動化金氧半動態臨限電壓技術
外文關鍵詞:Electronic Design AutomationDTMOS
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這篇論文敘述實現0.8V基體互補式金氧半動態臨限電壓技術設計低功率系統晶片應用。首先在第一章中先介紹半導體元件以及積體電路在SOC上的低電壓低功率消耗的趨勢。接著在第二章中介紹使用多重臨限電壓和動態臨限電壓技術的基體互補式金氧半動態臨限電壓元件,接下來使用電子設計自動化軟體,讓基體互補式金氧半動態臨限電壓元件設計系統單晶片。第三章藉由16位元的乘法器介紹使用基體互補式金氧半動態臨限電壓元件設計系統單晶片的後段設計中測試和分析,以及相關驗證程序。

The thesis describes the CHIP realization of 0.8v bulk CMOS DTMOS technique for optimization of low power system application. First, introduction on the low power, low voltage trends on CMOS SOC is described in chapter 1. Then a bulk PMOS DTMOS technique using MTCMOS and DTMOS technology is presented in chapter 2. Then the approach of chip realization in terms of integration of EDA tools for implementation an SOC chip using the bulk PMOS DTMOS technique is described. In chapter 3, detailed analysis of a test chip a 0.8v 16bit multiplier using the bulk PMOS DTMOS technique via the developed chip implementation technique using integrated EDA tools is described.

口試委員審定書..................... i

致謝................................ii

中文摘要...........................iii

ABSTRACT............................iv

目錄.................................v

圖目錄..............................vii

表目錄..............................ix


Chapter 1 導論.......................1

1.1矽互補式金氧半超大型積體電路的演化及發展趨勢.........1

1.2數位積體電路設計中EDA技術..........7

1.3電路的功率消耗分析....................10

1.4研究目標與論文架構....................13

Chapter 2 0.8V Bulk PMOS動態臨限電壓技術使用雙臨界電壓系統電路分析..14

2.1多重臨界電壓與動態臨限電壓技術....14

2.2 Bulk PMOS 動態臨限電壓矽金氧半元件技術.............16

2.3 Bulk PMOS 動態臨限矽金氧半元件邏輯閘電路...........19

2.4電子設計自動化......................23
2.4.1從Gate Level Netlist到自動佈局及繞線.............23
2.4.2使用BP-DTMOS-DT邏輯閘佈局以及繞線................25

Chapter 3 0.8V Bulk PMOS DTMOS 技術後段設計功率消耗分析以及驗證...........................................32

3.1功率消耗分析..............................32

3.2 DRC 與 LVS...............................37
Chapter 4 結論與未來研究方向...................42

參考文獻.......................................44


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