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研究生:黃信誠
研究生(外文):HSIN-CHENG HUANG
論文名稱:DPSK光解調變器特性探討
論文名稱(外文):The Optical DPSK Demodulator Study
指導教授:徐世祥
指導教授(外文):Shih-Hsiang Hsu
口試委員:徐世祥
口試日期:2011-07-26
學位類別:碩士
校院名稱:國立臺灣科技大學
系所名稱:光電工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2011
畢業學年度:99
語文別:中文
論文頁數:74
中文關鍵詞:解調變器差動相位偏移調變絕緣層上覆矽
外文關鍵詞:DemodulatorDPSKSOI
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近幾年光通訊系統為了有效增加系統容量及頻譜效率,提出許多先進訊號調變技術,這些技術是以開關調變及差動相位偏移調變為基礎,再加以變化衍伸的。傳統的開關調變系統在高速長距離傳輸過程會引起較嚴重的色散、極化模態色散及非線性效應。為了改善此類非線性現象,差動相位偏移調變系統相繼被提出且驗證,由於差動相位偏移調變在相位訊息上,每一位元擁有相同的功率,對因功率變化所引起的非線性效應,有較佳的容忍力,而達到改善的效果。
絕緣層上覆矽近年來廣泛應用於高速且低功耗電子元件,因為具有高折射率係數可大幅縮小元件體積,其製程方式與互補式金屬氧化物半導體製程相容,對發展光電積體電路有極大的潛力。本研究利用絕緣層上覆矽探討符合差動相位偏移調變的光通訊系統解調變元件。文中設計的解調元件為馬克-詹德干涉儀架構,由兩個2x2多模干涉耦合器中間包含延遲一個位元的路徑組成的延遲干涉儀,而主要影響延遲干涉儀輸出特性的參數為耦合器分光率、延遲路徑長度及延遲路徑損耗也會一並討論。另外,在文中首先討論2x2多模干涉器用於延遲干涉儀,其分光率在C+L頻帶(1530~1625 nm)保持(50.35?b0.35)%的輸出比例,同時極化相依損耗分別小於0.14dB。
在延遲干涉儀方面,設計10 Gb/s解調變元件所對應的延遲路經長度為8689.6 ?慆。當延遲路徑損耗極小時,利用2x2多模干涉器設計延遲干涉儀會得到良好的輸出特性,利用VPI模擬可得到DPSK(Differential Phase Shift Keying)系統Q值及消光比分別為62.69及23.81dB。以本實驗室目前的製程技術製作延遲路經,當路徑長為8689.6 ?慆造成的延遲路徑損耗為0.96 dB,依此條件代入VPI模擬系統Q值及消光比分別為62.32及21.54dB。因此,必須將前端2x2多模干涉器利用S型多模干涉器取代,在S型多模干涉器分光率55.5%時作功率補償,使延遲干涉儀達到最好的輸出特性,並由建設性輸出端得到優化後的DPSK系統Q值及消光比分別為62.73及23.93dB。
Optical telecommunication systems have been developed in order to increase the capacity and the spectral efficiency in the past few years. Some advanced modulation formats based on on-off-keying (OOK) and differential phase shift keying (DPSK) have been proposed. The conventional OOK format leads to serious impairments, such as chromatic dispersion (CD), polarization mode dispersion (PMD) or nonlinearity effect, in a high-speed long-haul transmission system. DPSK system has been developed and experimentally demonstrated to improve the nonlinear effect. Since the phase information have the same optical power for each bit in the DPSK system, the constant power transmission of DPSK induces more tolerant to the fiber nonlinearities.
The silicon-on-insulator (SOI) platform has been developed and demonstrated as a highly optoelectronic integrated circuits (OEIC) due to the large refractive index and its compatibility with the complementary metal oxide semiconductor (CMOS) standard process. In this thesis, the SOI will be utilized to make an optical DPSK demodulator, which is a Mach-Zehnder interferometer structure consisting of two 2x2 multi-mode interferometers (MMI) and 1 bit delay line, also known as a delay line interferometer (DLI). The main parameters which influence the output DLI performances are the 2x2 MMI splitting ratio, the delay line length, and the optical loss of 1 bit delay line. The 2x2 MMI was first discussed and demonstrated in DLI and its power splitting ratio of 2x2 MMI was keep in (50.35?b0.35)% over C + L band (1530~1625 nm) and the polarization dependent loss was less than 0.14 dB.
With respect to DLI, the length of 1 bit delay line of 10 Gb/s DPSK demodulator is 8689.6?慆. When the loss of 1 bit delay line is extremely small, the optimum output performances is happening on the 2x2 MMI as DLI optical power splitting. Q factor and extinction ratio are 62.69 dB and 23.81 dB, respectively, by utilizing VPI simulation software. From the preliminary optical loss data on the SOI waveguide fabricated in the Nano Facility Center (NFC), the loss of delay line was estimated as 0.96dB while the length was 8689.6?慆, and the Q factor and the extinction ratio are 62.32 dB and 21.54 dB, respectively, in the VPI simulation. To achieve optimum output characteristics, the 2x2 MMI at the input port should be replaced by S-bend MMI for the 55.5% power splitting ratio. The Q factor and the extinction ratio of the DPSK system are 62.73 dB and 23.93 dB in the constructive port, respectively.
摘要 I
Abstract II
致謝 IV
目錄 V
圖目錄 VII
表目錄 X
第一章 緒論 1
1.1 前言 1
1.2 研究動機 2
1.3 論文架構 3
第二章 差動相位偏移調變於光纖通訊系統應用 4
2.1 系統介紹 4
2.2 差動相位偏移調變原理 5
2.3 差動相位偏移解調變原理 9
2.4 差動相位偏移調變系統驗證 14
2.4.1 傳送端 14
2.4.2 接收端 16
第三章 波導理論 20
3.1 數值分析演算法 20
3.1.1 光束傳播法 20
3.1.2 有效折射率法 23
3.2 脊型波導之單多模條件 26
3.3 脊型波導損耗來源 29
3.3.1 耦合損耗 29
3.3.2 波導彎曲損耗 32
3.3.3 波導散射損耗 38
3.4 雙折射效應 39
3.5 多模干涉器 42
3.5.1 自我成像原理 42
3.5.2 多模干涉器的干涉機制 44
3.5.3 2x2多模干涉器模擬設計 48
第四章 DPSK解調變元件於SOI脊型波導設計 55
4.1 前言 55
4.2 延遲路徑的影響 55
4.3 非理想延遲干涉儀的影響 57
4.4 設計與優化 66
第五章 結論 71
參考文獻 72
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