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研究生:李昭憲
研究生(外文):Jau-hsien Li
論文名稱:全數位式鎖相迴路與時脈抖動自我量測電路
論文名稱(外文):An All Digital Phase-Locked Loop with A Jitter Measurement Built-In Self-Test Circuit
指導教授:林銘波林銘波引用關係
指導教授(外文):Ming-bo Lin
學位類別:碩士
校院名稱:國立臺灣科技大學
系所名稱:電子工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2010
畢業學年度:99
語文別:中文
論文頁數:46
中文關鍵詞:全數位式鎖相迴路自我量測電路
外文關鍵詞:all digital phase-locked loopBIST
相關次數:
  • 被引用被引用:1
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  • 下載下載:61
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傳統上為了加快全數位式鎖相迴路的鎖定速度,通常使用時間數位轉換器,在訊號剛輸入的前幾個週期中先計算出一粗略的值,控制震盪器輸出於相近的頻率,以增快鎖定速度。本論文則提供一個新的數位控制震盪器的架構,使得全數位式鎖相迴路不用加上時間數位轉換器,也能加快鎖定時間。此外,本論文提出一個簡單的內部自我量測時脈抖動的電路,以測量phase jitter與peak-to-peak jitter兩種時脈抖動。此電路的設計概念相當簡單,係以cell-based library 提供的數位邏輯閘,配合簡單的游標尺法與脈波縮減概念完成。
完成的晶片已經以TSMC 0.18 m CMOS 1P4M cell-based製程下線,核心面積330 m × 345 m,整體面積為1300 m × 1300 m,鎖相迴路鎖定範圍為70-495 MHz。時脈抖動量測電路解析度約為20 ps,phase jitter可量測的範圍約200 ps,可量peak-to-peak jitter的信號週期範圍為2 ns-50 ns。當操作頻率在100 MHz時,鎖相迴路與量測電路消耗功率為23.4 mW。
The time-to-digital converter (TDC) is widely used in ADPLL to speed up the locking time. The rationale behind this is to calculate a roughly control value so as to make the digital controlled oscillator (DCO) oscillate at a frequency near the input frequency. In this thesis, we propose a new DCO that has a faster locking time but does not need the use of TDC. In addition, in the thesis we present a built-in self-test (BIST) circuit for measuring two kinds of time jitter: phase jitter and peak-to-peak jitter. The design idea of the circuit is based on the techniques of vernier delay line (VDL) and pulse shrinking accompanying the gates from a cell-based design kit.
The resulting chip has been implemented by TSMC 0.18-μm CMOS cell-based design kit. The core area is 330 m × 345 m and the total area (with bounding PAD) is 1300 m × 1300 m. The measured results are as follows. The locking range of PLL is 70 MHz to 495 MHz; the resolution of BIST time jitter circuit is about 20 ps; the capture range of phase jitter is about ±200 ps; the capture range of peak-to-peak jitter is 2 ns to 50 ns. The power dissipation is 23.4 mW at the operating frequency of 100 MHz.
第一章 緒論 1
1.1 研究背景與動機 1
1.2 章節簡介 1
第二章 概要 2
2.1 混訊式鎖相迴路 2
2.1.1 相位頻率偵測器 3
2.1.2 電荷泵浦電路與低通濾波器 3
2.1.3電壓控制震盪器 4
2.1.4除頻器 4
2.2 全數位式鎖相迴路 4
2.2.1 相位頻率偵測器 5
2.2.2 控制單元 5
2.2.3 數位控制震盪器 5
2.2.4 除頻器 6
2.3 時脈抖動 7
2.3.1 Phase Jitter 7
2.3.2 Period Jitter and Peak-to-Peak Jitter 8
2.3.3 Cycle-to-Cycle Jitter 9
2.3.4 Long Term Jitter 10
2.4 量測時脈抖動 10
2.4.1 類比數位轉換 11
2.4.2 延遲線 12
2.4.3 游標尺 13
第三章 設計 14
3.1 全數位式鎖相迴路 14
3.1.1 相位頻率偵測器與除頻器 15
3.1.2 數位控制震盪器 16
3.1.3 控制單元 21
3.2 內部自我量測電路 23
3.2.1 選擇模式 24
3.2.2 脈波縮減區塊 25
3.2.3 由標尺區塊 30
3.2.4 控制電路區塊 33
3.2.5 測量phase jitter 34
3.2.6 測量peak-to-peak jitter 35
第四章 驗證 37
4.1 設計流程 37
4.2 測試考量 37
第五章 結論 44
參考文獻 45
[1]Ching-Che Chung, and Chen-Yi Lee. An all-digital phase-locked loop for high-speed clock generation. IEEE Journal of Solid-State Circuits, VOL.38, P347-351. February 2003.
[2]Chua-Chin Wang, Chi-Chun Huang, and Sheng-Lun Tseng. A low-power ADPLL using feedback DCO quarterly disabled in time domain. Microelectronics Journal, ISSN: 00262692, VOL.39, P832-840. February 2008.
[3]Thomas Olsson, and Peter Nilsson. A digitally controlled PLL for digital SOCs. IEEE International Symposium on Circuits and Systems, VOL5, V-437 - V-440. May 2003.
[4]Tian Xia, Stephen Wyatt, and Rupert Ho. Employing On-Chip Jitter Test Circuit for Phase Locked Loop Self-Calibration. IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT '06. October 2006.
[5]Brandon Ray Kam. (VDL)2:A jitter measurement built-in self-test circuit for phase locked loops. Degree of Master of Engineering in Electrical and Computer Science at the Massachusetts Instute of Technology. January 2005.
[6]Mike Peng Li, Jitter. Noise, and Signal Integrity at High-Speed, Adobe Reader. Published by Prentice Hall. October 2007.
[7]M.A.Abas, G..Russell, and D.J.Kinniment. Design of sub-10-picoseconds on-chip time measurement circuit. Automation and Test in Europe Conference and Exhibition Design. VOL.2, P804-809. 2004.
[8]Antonio H. Chan, and Gordon W. Roberts. A synthesizable, fast and high-resolution timing measurement device using a component-invariant vernier delay line. International Test Conference, P858-867. October 2001.
[9]Tian Xia, and Jien-Chung Lo. On-chip jitter measurement for phase locked loops. IEEE International Symposium on Publication Defect and Fault Tolerance in VLSI Systems DFT 2002, P399-407. November 2002.
[10]Poki Chen, Shen-Luan Liu,and Jingshown Wu. A CMOS pulse-shrinking delay element for time interval measurement. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, Vol.47, P.954-958. September 2000.
[11]Dean Banerjee, PLL performance simulation and design, ISBN: 0970820712
[12]鄭仲凱, 全數位式鎖相迴路智財設計與驗證 The design and Verification of an ADPLL IP. 國立台灣科技大學電子工程研究所碩士論文. 中華民國九十六年十月.
[13]陳文華, 鎖相迴路(PLL)原理與應用. 全華科技圖書股份有限公司. 中華民國72年9月.
[14]遠?筍T昭, PLL電路設計及應用. 全華科技圖書股份有限公司. 中華民國95年9月
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