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研究生:謝名峻
研究生(外文):MING-CHUN HSIEH
論文名稱:可選擇金鑰之低成本AES晶片設計
論文名稱(外文):Low Cost Design of Optional Key AES Chip
指導教授:林銘波林銘波引用關係
指導教授(外文):Ming-bo Lin
學位類別:碩士
校院名稱:國立臺灣科技大學
系所名稱:電子工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2010
畢業學年度:99
語文別:中文
論文頁數:79
中文關鍵詞:先進加密標準Rijndael演算法即時運算模式金鑰擴展單元位元組替代轉換混合行運算
外文關鍵詞:AESRijndael algorithmon-the-flykey expansions-boxmix-column
相關次數:
  • 被引用被引用:2
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  • 下載下載:46
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論文中提出了一個低成本架構的AES加解密晶片,並且金鑰擴展單元為較省面積的即時運算架構,且能夠依使用者來選擇金鑰的長度,分別為128位元、192位元以及256位元。且依據AES演算法實現出來的加解密晶片輸入的每一筆資料為128位元。為了能夠有效節省面積,在資料路徑的部分我們使用長度為32位元的架構。因此,每一筆128位元長度的資料配合一筆完整的金鑰,計算每一回合需要4個時脈週期方能完成。更進一步的達到節省面積,我們在回合運算單元中,改進了兩個部分:在位元組替代轉換中,使用混合場運算來有效的降低演算法複雜度,進而減低硬體面積;混合行轉換中,將演算法簡化之後,再找出相同的運算子來達到電路共享,因此也能有效節省面積,而相較於傳統的AES架構,最大可節省將近一半的邏輯閘數量。
AES加解密軟智產已經分別在Xilinx的Vertex 5系列FPGA(xc5vlx110t)以及TSMC 0.18 μm元件庫(Cell Library)上實現與驗證。在FPGA設計部分,工作頻率為60 MHz,資料處理量最高為174.54 Mbps,消耗了Vertex 5系列FPGA實驗板總面積的7%;在元件庫設計的部分,工作頻率為106 MHz,資料處理量最高為308.36 Mbps,核心(core)面積為517.6 μm × 508.3 μm,其等效閘數量(gate count)約為15669個,消耗功率為21.22 mW。
In the thesis, we propose an area-saving universal VLSI architecture for AES encryption/decryption algorithm. To be used as a universal AES encryption/ decryption system and be able to accept a key with three different lengths, 128, 192, and 256 bits, the data-path of proposed architecture is designed as 32 bits and the keys are computed on-the-fly by the key expansion unit. As a consequence, for each 128-bit input with the cipher key, to finish a single round operation needs 4 clock cycles. The area of the proposed architecture is further reduced by the following two improvements. First, the composite field arithmetic is used for the byte substitution transformation to effectively reduce the complexity of algorithm. Second, the common operation is employed in the mix column transformation to achieve the circuit sharing and hence to reduce the area. The resulting architecture can save about a half area in comparison with conventional AES architecture.
The AES encryption/decryption chip has been implemented and verified with both Xilinx Vertex 5 FPGA and TSMC 0.18 μm cell library. In the FPGA part, it operates at 60 MHz and can achieve a high throughput of 174.54 Mbps. It takes up the total area of 7% in FPGA board. In the cell-based part, it operates at 106 MHz and can achieve a high throughput of 308.36 Mbps. The core occupies the area of 517.6 μm × 508.3 μm, which is approximately equivalent to 15669 gates, and consumes about 21.22 mW in the typical operating condition.
摘要 i
誌謝 iii
目錄 iv
表目錄 vii
圖目錄 viii
第一章 緒論 1
1.1 簡介 1
1.2 研究方向 2
1.3 章節安排 3
第二章 AES加解密演算法介紹 4
2.1 對稱式與非對稱式密碼系統 5
2.1.1 對稱式密碼系統 5
2.1.2 非對稱式密碼系統 5
2.2 AES的演進與名詞定義 7
2.2.1 AES的演進 7
2.2.2 Rijndael演算法名詞定義 8
2.3 數學知識 10
2.3.1 有限場 10
2.3.2 加法 10
2.3.3 乘法 11
2.3.4 乘以x 12
2.4 Rijndael演算法規範 12
2.4.1 加密演算法 14
2.4.2 金鑰擴展程序 19
2.4.3 解密演算法 21
2.4.4 等價解密演算法 25
第三章 AES硬體架構分析與改進 27
3.1 對稱區塊碼架構介紹 27
3.1.1 循環展開式 29
3.1.2 外部回合管線式 30
3.1.3 內部回合管線式 31
3.1.4 混合內部與外部回合管線式 32
3.2 回合運算單元 34
3.2.1 位元組替代轉換模組 35
3.2.2 列位移轉換模組 42
3.2.3 混合行轉換模組 44
3.2.4 加入回合金鑰模組 47
3.3 金鑰擴展單元 48
3.3.1 設計方法比較與分析 48
3.3.2 金鑰擴展單元核心架構 49
第四章 AES加解密晶片設計 54
4.1 核心運算單元 56
4.2 資料暫存器單元 57
4.3 控制單元 58
第五章 FPGA設計之實現與結果分析 60
5.1 RTL設計與模擬 60
5.2 FPGA實體驗證 64
5.2.1 FPGA設計流程 64
5.2.2 AES加解密晶片之FPGA設計 65
5.2.3 AES加解密晶片之FPGA驗證 66
第六章 元件庫設計之實現與效能評估 69
6.1 元件庫設計與驗證結果 70
6.1.1 RTL-Level Simulation 70
6.1.2 Gate-Level Simulation 70
6.1.3 ATPG測試考量 70
6.1.4 晶片佈局與佈局後模擬結果 71
6.2 晶片效能分析 73
第七章 結論 76
參考文獻 77
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