臺灣博碩士論文加值系統

　　本論文為一個具有自我校準功能並以脈衝擴展法為基礎之時間至數位轉換器，脈衝擴展器以雙斜率法實現，並搭配循序漸進暫存器達到自我校準的功能，以降低環境溫度、製程參數、工作電壓等環境變異所造成之誤差，使脈衝擴展法時間至數位轉換器的量測精準度不易受到周圍環境的改變而變化。
　　本時間至數位轉換器之解析度高達3.9ps，核心電路面積為0.77×0.25 mm2，消耗功率為15.4mW，以TSMC 1P6M 0.18μm的製程實現，模擬結果指出，在五個製程參數變異、電壓變異1.62V到1.98V與溫度變異0℃到100℃的環境下皆可藉由自我校準功能將擴展因子調整至預期規格需求。

This paper provides a TDC based on pulse stretch method possesses self calibration technique. The pulse stretcher is implemented by dual-slope method. The self calibration technique uses Successive-Approximation Register (SAR) to reduce the error from process, supply voltage and ambient temperature (PVT) variation. Therefore, the precision and accuracy have low sensitivity of PVT variation.
The resolution of proposed TDC reaches 3.9ps. Die area is 0.77×0.25 mm2. The power consumption is 15.4mW. The process is TSMC 1P6M 0.18μm. According to the simulation result, under process variation, supply voltage variation over 1.62V to 1.98V and ambient temperature variation over 0℃ to 100℃, the stretch factor tallies the requirement of anticipated specification.

目錄

中文摘要………………………………………………………………………I
英文摘要………………………………………………………………………II
誌　　謝………………………………………………………………………III
目　　錄………………………………………………………………………IV
圖 目 錄………………………………………………………………………VII
表 目 錄………………………………………………………………………XI

第一章 緒論…………………………………………………………………….1
1.1 研究動機……………………………………………………………………1
1.2 內容編排方式………………………………………………………………3

第二章 時間至數位轉換器…………………………………………………….4
2.1 時間至數位轉換器簡介……………………………………………………4
2.2 計數器法之時間至數位轉換器……………………………………………5
2.3 脈衝縮減延遲法之時間至數位轉換器……………………………………8
2.3.1 線性脈衝延遲法……………………………………8
2.3.2 循環式脈衝縮減法…………………………………9
2.3.3　非均質與均質脈衝縮減延遲線…………………10
2.4 場可程式化閘陣列為主體之時間至數位轉換器……………………….12
2.5 游標卡尺法之時間至數位轉換器……………………………………….15

第三章 具3.9微微秒解析度之自我校準式時間至數位轉換器…………….19
3.1脈衝擴展法之時間至數位轉換器…………………………………………20
3.2具3.9微微秒解析度之自我校準式時間至數位轉換器………………….22
3.3時間至脈衝控制電路………………………………………………………23
3.3.1時間至脈衝控制電路介紹…………………………23
3.3.2介穩態………………………………………………27
3.4脈衝擴展器(內插器)………………………………………………………30
3.5具3.9微微秒解析度之自我校準式脈衝擴展器………………………….34
3.5.1自我校準式脈衝擴展器工作原理…………………34
3.5.2內插器開關切換之誤差……………………………38
3.5.3放電電容間之寄生耦合電容………………………43
3.5.3.1放電電容間耦合電容之解決方法………………43
3.5.4有限的電流源輸出阻抗……………………………45
3.5.5循序漸進暫存器(SAR)…………………………….47
3.5.6比較器………………………………………………50
3.5.6.1比較器概論………………………………………50
3.5.6.2比較器原理說明…………………………………51
3.5.6.3比較器之架構……………………………………55
3.5.7計數器………………………………………………58

第四章 電路模擬與晶片佈局…………………………………………………59
4.1設計流程與考量……………………………………………………………59
4.2具3.9微微秒解析度之自我校準式時間至數位轉換器模擬及驗證……………………………………………………………………………….61
4.2.1時間至脈衝控制電路模擬…………………………62
4.2.2循序漸進暫存器(SAR)模擬……………………….64
4.2.3具自我校準之脈衝擴展器模擬……………………66
4.2.4比較器模擬…………………………………………72
4.2.5計數器模擬…………………………………………74
4.2.6時間至數位轉換器系統模擬………………………75
4.3 晶片佈局…………………………………………………………….80

第五章 量測考量………………………………………………………………82
5.1量測環境……………………………………………………………………82
5.2量測方法……………………………………………………………………85

第六章 結論與未來展望………………………………………………………88
6.1 文獻比較………………………………………………………………….88
6.2 未來展望………………………………………………………………….90

參考文獻……………………………………………………………………...92

參考文獻

[1]E. Raisanen-Ruotsalainen, T. Rahkonen, and J. Kostamovaara,“A Low-Power CMOS Time-to-Digital Converter,”　IEEE Journal of Solid-State Circuits, vol.30, no.9,　pp.984-990, Sept. 1995.
[2]K. Maatta, and J. Kostamovaara, “A High-Precision Time-to-Digital　Converter for Pulsed Time-of-Flight Laser RadarApplications,” IEEE Transactions on Instrumentation and Measurement, vol.47, no.2, pp.521-536, April 1998.
[3]E. Raisanen-Ruotsalainen, T. Rahkonen, and J. Kostamovaara, “An Integrated Time-to-Digital Converter with 30-ps Single-Shot Precision,” IEEE Journal of Solid-State Circuits, vol.35, no.10, pp.1507-1510, Oct. 2000.
[4]R. W. Necoechea, “High performance monolithic verniers for VLSI automatic test equipment,” Proceedings International Test Conference, pp. 422-30, 1992.
[5]T. Otsuji, “A picosecond-accurary, 700-Mhz range si-bipolar time interval counter LSI, ”IEEE J. Solid-State Circuit, vol.28, pp.941-947, Sept.1993.
[6]R. Nutt, “Digital Time Intervalometer,” Rev. Sci. Instrum, vol.39, no.9, pp.1342-1345, 1968.
[7]I. Nissinen, A. Mantyniemi, and J. Kostamovaara, “A CMOS Time-to-Digital Converter based on a Ring Oscillator for a Laser Radar,” In proc.ESSCIRC 2003, pp. 469-472, Sept. 2003.
[8]P. Chen, C.-C. Chen, and Y.-S. Shen, “A Low-Cost Low-Power CMOS Time-to-Digital Converter Based on Pulse Stretching,” IEEE Transactions on Nuclear Science, vol.53, no.4, pp.2215-2220, Aug.2006.
[9]P. Chen, S.-I. Liu, and J. Wu, “Highly Accurate Cyclic CMOS Time-to-Digital Converter with Extremely Low Power Consumption,” IEEE Electronics Letters, vol.33, no.10, pp.858-860, May 1997.
[10]Wei Chang, Mao-Hsing Chiang and Poki Chen, “A Highly Accurate Cyclic CMOS Time-to-Digital Converter with Temperature Compensation”, The 14th VLSI Design/CAD Symposium, Aug. 2003.
[11]J. Kalisz, R. Szplet, J. Pasierbinski, and A. Poniecki, “Field-Programmable-Gate-Array-Based Time-to-Digital Converter with 200-ps Resolution,” IEEE Transactions on Instrumentation and Measurement, vol.46, no1, pp.51-55, Feb. 1997.
[12]J. Song, Q. An, and S. Liu, “A High-Resolution Time-to-Digital Converter Implemented in Field-Programmable-Gate-Arrays” IEEE Transactions on Nuclear Science, vol.53, no.1, pp.236-241, Feb. 2006.
[13]M.s. Gobrics, J. Kelly, K.M. Roberts and R.L. Summer, “A high resolution multihit time to digital converter integrated circuit,” IEEE Transaction on Nuclear Science, vol. 44, pp. 379-384, June. 1997.
[14]N. Abaskharoun, M. Hafed and G.W. Roberts, “Strategies for on-chip sub-nanosecond signal capture and timing measurements,” International Symposium on Circuits and Systems, vol. 4, pp. 174-177, May 2001.
[15]P. Dudek, S. Szczepanski and J.V. Hatfield, “A higresolution CMOS time-to-digital converter utilizing a Vernier delay line” IEEE Journal of Solid-State Circuits, vol. 35, no. 2, pp. 240-247, Feb. 2000.
[16]T. Rahkonen and J. Kostamovaara, “The use of stabilized CMOS delay line for the digitization of short time intervals,” IEEE Journal of Solid-State Circuit, vol. 28, pp.887-894, Aug. 1993.
[17]C. T. Gray, W. Liu, W. A. M. Van Noije, T. A. Hughes Js and R. K. Cavin III, “A sampling technique and its CMOS implementation with 1 Gbs bandwidth and 25ps resolution,” IEEE Journal of Solid-State Circuits, vol. 29, pp.340-349, Mar. 1994.
[18]V. Ramakrishnan and P.T. Balsara, “A wide-range, high-resolution, compact, CMOS Time to Digital Converter” IEEE Proceedings of the 19th International Conference on VLSI Design, Jan. 2006.
[19]Poki Chen, Jia-Chi Zheng and Chun-Chi Chen, “A Monolithic Vernier-Based Time-to-Digital Converter with Dual PLLs for Self-Calibration,” IEEE Custom Integrated Circuits Conference, pp.321-324, Sept. 2005.
[20]Poki Chen, Chun-Chi Chen, Jia-Chi Zheng and You-Sheng Shen, “A PVT Insensitive Vernier-Based Time-to-Digital Converter with Extended Input Range and High Accuracy,” IEEE Transaction on Nuclear Science, vol. 54, no. 2, Apr. 2007.
[21]E. Owen, “The Elimin ation of offset Errors in Dual-slope Analog-to-Digital Converters,” In proc.IEEE Trans. Circuits Syst., vol. 27, no. 2, pp. 137-141, Feb. 1990.
[22]B.K. Swann, B. J. Blalock, L. G. Clonts, D. M. Binkley, J. M. Rochelle, E. Breeding, and K. M. Baldwin, “A 100ps Time-Resolution CMOS Time-to Digital Converter for Positron Emission Tomography Imaging Applications,” IEEE J. Solid-State Circuits, vol. 39, no. 11, pp. 1839-1852, Nov. 2004.
[23]Kihyuk Sung; Lee-Sup Kim, “A high-resolution synchronous mirror delay using successive approximation register, ” Volume 39, no. 11, pp. 1997-2004, Nov. 2004.
[24]Rossi, A.; Fucili, G. “Nonredundant successive approximation register for A/D converters, ” Electronics Letters Volume 32, no. 12, pp. 1055 – 1057 June 1996.
[25]Russell, H., Jr. “An improved successive-approximation register design for use in A/D converters, ” IEEE CAS-I, vol. 25, no. 7, pp. 550-554, Jul. 1978.
[26]J. Kostamovaara and R. Myllylä, “Time-to-digital converter with an analog interpolation circuit,” Rev. Sci. Instrum., vol.57, pp. 2880-2885, 1986.
[27]Poki Chen, Chun-Chi Chen and You-Sheng Shen, “A Low Cost Low Power CMOS Time-to-Digital Converter Based on Pulse Stretching,” IEEE Transaction on Nuclear Science, vol. 53, no. 4, pp. 2215-2220, Aug. 2006.
[28]Minkyu Song, Yongman Lee and Wonchan Kim, “A clock feedthrough reduction circuit for switched-current systems, ” IEEE Journal of Solid-State Circuits, vol. 28, no.2, pp. 133-137, Feb. 1993.
[29]M. Helfenstein and G.S. Moschytz, “Improved two-step clock-feedthrough compensation technique for switched-current circuits,” IEEE Transactions on Circuits and Systems II, vol.45, no. 6, pp.739-743, June. 1998.
[30]Behzad Razavi, “Design of Analog CMOS Integrated Circuits,” McGraw-Hill, 2001.
[31]A. Rossi, and G. Fucili, “Nonredundant Successive Approximation Register for A/D Converters,” IEEE Electronics Letters, vol. 32, no. 12, pp.1055-1057, June 1996.
[32]David A. Johns and Ken Martin, “Analog Integrated Circuit Design,” Wiley, Canada, 1997.
[33]D.J. Allstot, “A Precision Variable-Supply CMOS Comparator,” IEEE Journal of Solid-State Circuits, vol. 17, Issue 6, pp.1080-1087, Dec 1982.
[34]E. Allen and R. Holberg, “CMOS Analog Circuit Design second edition,” Oxford, New York, 2002.
[35]Chorng-Sii Hwang, Poki Chen and Hen-Wai Tsao, “A high-precision time-to-digital converter using a two-level conversion scheme,” IEEE Transaction on Nuclear Science, vol. 51, pp. 1349-1352, Aug. 2004.
[36]J. P. Janson et al., “A CMOS time-to-digital converter with better than 10 ps single-shot precision,” IEEE J. Solid-State Circuits, vol. 41, no. 6, pp. 286–1296, Jun. 2006.
[37]K. Karadamoglou, N. P. Paschalidis, E. Sarris, N. Stamatopoulos, G. Kottaras, and V. Paschalidis, “An 11-bit high-resolution and adjustable-range CMOS time-to-digital converter for space science instruments,” IEEE J. Solid-State Circuits, vol. 39, pp. 214-222, Jan. 2004.
[38]G. Van Der Plas, J. Vandenbussche, W. Sansen, M. Steyaert and G. Gielen, “A 14-bit intrinsic accuracy Q2 random walk CMOS DAC,” IEEE Journal of Solid-State Circuits, vol. 34, pp.1708-1717, Dec. 1999.
[39]M. Vadipour, “Gradient error cancellation and quadratic error reduction in unary and binary D/A converters,” IEEE Transactions on Circuits and Systems II, vol. 50, pp.1002-1007, Dec. 2003.
[40]M.A.P. Pertijs, A. Bakker and Huijsing, J.H. “A high-accuracy temperature sensor with second-order curvature correction and digital bus interface,” IEEE Proceedings of the International Symposium on Circuits and Systems, vol.1, pp. 368-371, May 2001.
[41]Ming-Chan Weng and Jiin-Chuan Wu, “A Temperature sensor in 0.6μm CMOS Technology,” IEEE Asia Pacific CNF, pp. 116-119, Aug.1999.
[42]Poki Chen, Kai-Ming Wang, Chuan-Yuan Li, Po-Yu Chen, Juan-Shan Lai and Cheng-Wei Liu, “CMOS Time-to-Digital Converter with Low PVT Sensitivity 20.8ps Resolution and -0.25~0.22 LSB Inaccuracy,” IEEE International Conference on Anti-counterfeiting, Security, and Identification (ASID), to be published, Xiamen, China, June 2011. (Keynote Speech)