臺灣博碩士論文加值系統

由於無線通訊系統的發展，具有數個百萬赫茲頻寬的類比數位轉換器受到大量的需求，三角積分調變器理想上適合這樣的應用。相較於離散時間切換電容電路的實現方式，連續時間三角積分調變器擁有更寬頻的潛力同時也天生具有抗混疊的特性。
在本論文，兩個連續時間三角積分調變器被設計與製作，第一個是應用於WiMAX的四相位帶通三角積分調變器。電容式前饋在這個電路被應用於頻率補償。相較於傳統CIFF架構，電容式前饋是一種簡單的實現方式。時脈為160 MHz的情況下，在一個10MHz的頻寬內這個調變器量測到46 dB的動態範圍，SNDR為37 dB，IM3為-44 dB。在1.8 V的電源下量測的功率消耗是41.5 mW。包含Pads的晶片面積是1.7947 (1.31 x 1.37) mm2。
雖然三角積分調變器能容忍類比電路的不完美特性，但其輸出需要經過抽
取濾波器。另一方面，帶通三角積分調變器的特性不受低頻雜訊的影響，但其輸出需要在數位領域做降轉換。為了示範一個完整的四相位帶通三角積分類比數位轉換器，適用於四相位帶通三角積分調變器的抽取濾波器被設計並模擬。
第二個調變器晶片是一個具有混合主動與被動迴路濾波器的連續時間三角積分調變器，可應用於WCDMA。其中的五階迴路濾波器主要由兩個被動濾波器與三個主動濾波器構成。另外，為了移除一個被用在CIFF架構的加總放大器，電容式前饋架構同樣被使用。區域回授電阻亦使用橋式Ｔ網路來建構以減小佈局面積。使用TSMC 0.18 um 1.8 V CMOS製作後，在2 MHz的頻寬內晶片量測到62 dB的動態範圍，SNDR為60.26 dB，IM3為-48 dB。功率消耗為9 mW。包含pad的總晶片片積為0.642 ( 1.07 x 0.6) mm2。

With increasing development of wireless communication systems, there is a large demand in the wireless communication for analog-to-digital converters (ADCs) that require signal bandwidths of several megahertz. Sigma-delta modulators (ΣΔ modulators) are ideally suitable for such applications. Compared to the discrete-time switched capacitor circuit implementations, continuous-time (CT) ΣΔ modulators have the potentials for wider bandwidth and are also inherent anti-aliasing.
In this thesis, two CT ΣΔ modulators were designed and fabricated. The first one is the complex bandpass ΣΔ modulator for WiMAX application. Capacitive feedforward are employed for frequency compensation. Capacitive feedforward is a simple solution compared to conventional CIFF (chain of integrators with weighted feedforward summation) topology. Clock at 160 MHz, The modulator achieved a measured dynamic range of 46 dB over a 10 MHz signal bandwidth, SNDR of 37 dB, IM3 of -44 dB. The measured power dissipation is 41.5 mW from a 1.8 V supply voltage. Including pads, the chip occupies 1.7947 (1.31 x 1.37) mm2.
Although ΣΔ modulators tolerate to imperfection of analog circuit, the decimation and filtering of the output stream of ΣΔ modulators are necessary. In addition, the performance of bandpass ΣΔ modulators is not interfered by low frequency noise, however, downconversion of the output stream in digital domain is needed. To demonstrate a complete complex bandpass ΣΔ ADC, decimation filter for complex bandpass ΣΔ modulator is designed and simulation results are given.
The second modulator chip is the CT ΣΔ modulator with a hybrid active-passive loop filter for WCDMA application. This 5th-order loop filter architecture mainly consists of two passive integrators and three active integrators. Also, to erase the summation amplifier used in the CIFF topology, the capacitive feedforward structure is also employed. In addition, local feedback resistors are formed as the bridge-T network to reduce the chip area. After chip being fabricated in TSMC 0.18 um 1.8 V CMOS technology, the overall measured results have achieved dynamic range of 62 dB over a 2 MHz signal bandwidth, SNDR of 60.26 dB, IM3 of -48 dB and power dissipation of 9 mW. Including pads, the overall chip area is 0.642 (1.07 x 0.6) mm2

誌謝 　
Abstract (in Chinese)
Abstract (in English)
Contents
List of Figures
List of Tables
Chapter 1 Introduction
1.1 Motivation
1.2 Organization
Chapter 2 Basic Concepts of Delta Sigma Modulator
2.1 Introduction
2.2 Analog to Digital Conversion
2.3 Delta Sigma Modulation
2.3.1 Oversampling
2.3.2 Noise-Shaping ΔΣ ADC
2.3.3 Multi-Bit ΔΣ Modulator
2.3.4 Dynamic Element Matching
2.3.5 Continuous-Time and Discrete-Time Loop Filter
2.4 Frequency Compensation by Capacitive Feedforward
2.4.1 Feedback Compensation
2.4.2 Feedforward Compensation
2.4.3 Feedforward Compensation by Capacitive Feedforward
2.5 Performance Metrics
2.6 Paper Survey
2.7 Summary
Chapter 3 The Continuous-Time Complex Bandpass Sigma-Delta Modulator Chip Design for WiMAX Application
3.1 Introduction
3.2 Complex Bandpass modulator
3.2.1 Complex Signal
3.2.2 Complex Filter
3.2.3 Complex Noise Transfer Function
3.2.4 Complex ΔΣM Architecture
3.3 Design of Continuous Time Complex Bandpass Delta Sigma Modulator
3.3.1 Specification
3.3.2 Architecture
3.3.3 Coefficient Design
3.4 Effects of Non-Idealities on Complex Modulator Performance
3.4.1 Finite Gain and Finite Bandwidth of Op Amp
3.4.2 RC Product Variation
3.4.3 Clock Jitter
3.4.4 Excess Loop Delay
3.4.5 DAC Element Mismatch
3.4.6 Channel Mismatch
3.5 Circuit Implementation
3.5.1 3rd Order Complex Filter
3.5.2 Op Amp
3.5.3 Quantizer
3.5.4 Current Steering DACs for Global Feedback
3.5.5 Current Steering DACs for Local Feedback
3.5.6 Data Weighted Averaging
3.5.7 Bandgap Reference
3.6 Layout Consideration
3.7 Simulation Results
3.7.1 Simulation of Output Swing of Op Amp
3.7.2 Simulation of Non-idealities on Modulator Performance
3.7.3 Simulation of Output Spectrum and Dynamic Range
3.8 Measurement Results
3.7.1 Chip Photograph
3.7.2 Measurement Setup
3.7.3 Measurement Results
3.9 Summary
Chapter 4 Decimation Filter for Complex Bandpass Sigma-Delta Modulator
4.1 Introduction
4.2 System Description and Specifications
4.2.1 DC Offset Correction
4.2.2 CIC Decimation Filter
4.2.3 Digital Complex Mixer
4.2.4 Halfband Filter
4.3 Circuit Implementation
4.3.1 Reduction of Hardware Complexity with Truncation
4.3.2 1-bit Full Adder
4.3.3 D Flip-Flop
4.3.4 1-bit Integrator and Differentiator
4.3.5 Cascaded Integrator and Comb Filter
4.3.6 12-bit Signed Array Multiplier
4.3.7 Halfband Filter
4.4 Simulation Results
4.5 Summary
Chapter 5 Chip Design of The CT Sigma-Delta Modulator with a Hybrid Active-Passive Loop Filter
5.1 Introduction
5.2 Design and Architecture of the Hybrid ΣΔ modulator
5.3 Effects of Non-Idealities on Hybrid Modulator Performance
5.3.1 Effect of Non-Ideal Opamp
5.3.2 RC Product Variation
5.3.2 Clock Jitter
5.4 Circuit Implementation
5.4.1 Op Amp
5.4.3 Dynamic Comparator and D-latch
5.4.4 DAC
5.5 Simulation Results
5.6 Measurement Results
5.7 Summary

Chapter 6 Conclusions
7.1 Thesis Conclusion
7.2 Future Work
Bibliography
Appendix

[1] R. Schreier and G. C. Temes, Understanding Delta-Sigma Data Converters, Piccataway, NJ: IEEE Press, 2005.

[2] H. Shibata, D. Paterson, S. R.. Schreier, N. Abaskharoun,e, I. Mehr, and Q. Luu, “A 375-mW quadrature bandpass Delta Sigma ADC with 8.5-MHz BW and 90-dB DR at 44 MHz,” IEEE J. Solid-State Circuits, vol. 41,no. 12, pp. 2632–2640, Nov. 2009.

[3] Z. Li and T. S. Fiez, "A 14-bit continuous-time delta-sigma A/D modulator with 2.5 MHz signal bandwidth," IEEE J. Solid-State Circuits, vol. 42, pp. 1873-1883, Sep. 2007.

[4] W. Yang, W. Schofield, H. Shibata, S. Korrapati, A. Shaikh, N. Abaskharoun,
and D. Ribner, ”A 100mW 10 MHz-BW CT ΔΣ Modulator with 87dB DR and
91dBc IMD,” ISSCC Dig. Tech. Papers , 2008, pp. 498–499

[5] L. Dorrer, F. Kuttner, P. Greco, P. Torta, and T. Hartig. “A 3-mW 74-dB SNR 2-MHz continuous-time delta-sigma ADC with a tracking ADC quantizer in 0.13-μm CMOS,” IEEE J. Solid-State Circuits, vol. 40, pp. 2416-2427, Dec. 2005.

[6] R. Schreier, N. Abaskharoun, H. Shibata, D. Paterson, S. Rose, I. Mehr, and Q. Luu, “A 375-mW Quadrature Bandpass Delta Sigma ADC With 8.5-MHz BW and 90-dB DR at 44 MHz,” IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 2632-2640, Dec. 2006.

[7] B. Javid, “Low-Power Delta-Sigma A/D Design for Broadband Applications,” Master Thesis, Toronto University, 2006.

[8] F. Medeiro, A. Perez-Verdu, and A. Rodriguez-Vazquez, Top-Down Design of High-Performance Sigma-Delta Modulators, Kluwer Academic Publishers, 1999.

[9] G. I. Bourdopoulos, A. Pnevmatikakis, V. Anastassopoulos, and T. L. Deliyannis, Delta-Sigma Modulators, Imperial College Press, 2009.

[10] B. C. Nordick, “Dynamic element matching techniques for delta-sigma ADCs with large internal quantizers,” Master Thesis, Brigham Young University, 2004.

[11] Z. Li, “Design of a 14-bit continuous-time delta-sigma A/D modulator with 2.5MHz signal bandwidth,” Ph.D. Thesis, Oregon State University, 2006.

[12] Paulo G. R. Silva and Johan H. Huijsing, High-Resolution IF-to-Baseband Sigma-Delta ADC for Car Radios, Springer, 2008

[13] M. Ortmanns and F. Gerfers, Continuous-Time Sigma-Delta A/D Conversion, New York: Springer, 2006.

[14] A. Marques, V. Peluso, M. S. Steyaert, and W. M. Sansen, “Optimal Parameters for ΔΣ Modulator Topologies,” IEEE Trans. Circuits Syst. II, vol. 45, No. 9, pp. 1232-1241, Sept. 1998.

[15] S. B. Kim, S. Joeres, R. Wunderlich, and S. Heinen, “A 2.7 mW, 90.3 dB DR Continuous-Time Quadrature Bandpass Sigma-Delta Modulator for GSM/EDGE Low-IF Receiver in 0.25 um CMOS,” IEEE J. Solid-State Circuits, vol. 44, no. 3, pp. 891-900, Mar. 2009.

[16] L. J. Breems, R. Rutten, R.H. M. van Veldhoven, and G. van der Weide, “A 56 mW Continuous-Time Quadrature Cascaded Delta Sigma Modulator With 77 dB DR in a Near Zero-IF 20 MHz Bandwidth,” IEEE J. Solid-State Circuits, vol. 42, no. 12, pp. 2696-2705, Dec. 2007..

[17] B. Pandita and K. W. Martin, “Oversampling A/D Converters With Reduced Sensitivity to DAC Nonlinearities,” IEEE Trans. Circuits Syst. II, vol. 56, no. 11,pp. 840–844, Dec. 2009.

[18] S. B. Kim, S. Joeres, N. Zimmermann, M. Robens, R. Wunderlich, and S. Heinen, “Continuous-time quadrature bandpass sigma-delta modulator for GPS/Galileo low-IF receiver,” in Proc. 2007 IEEE Int. Workshop on Radio-Frequency Integration Technology, Singapore, Dec. 2007, pp. 127–130.

[19] Mobile WiMAX – Part I: A Technical Overview and Performance Evaluation, http://www.wimaxforum.org/technology/downloads/Mobile_WiMAX_Part1_Overview_and_Performance.pdf

[20] L. Breems and J. H. Huijsing, Continuous Time Sigma Delta Modulation for A/d Conversion in Radio Receivers, Springer, 2001.

[21] F. Munoz, “A 4.7 mW 89.5 dB DR CT Complex DS ADC with Built-in LPF,” IEEE ISSCC Dig. Tech. Papers, pp. 500-501, Feb. 2005.

[22] M. S. Kappes, “A 2.2-mW CMOS Bandpass Continuous-Time Multi-bit ΔΣ ADC with 68 dB of Dynamic Range and 1-MHz Bandpass for Wireless Applications,” IEEE J. Solid-State Circuits, vol. 38, no. 7, pp. 1098-2003, Jul. 2003.

[23] V. Peluso, A. Marquez, M. Steyaert, and W. Sansen, “Optimal Parameters for Single Loop ΣΔ modulator,” IEEE International Sym. on Circuit and Systems, pp. 57-60, June 1997.

[24] N. Yaghini, Design of a Wideband Quadrature Continuous-Time Delta-Sigma ADC, M.S thesis, University of Toronto, 2004.

[25] A. Van den Bosch, M. Borremans, S. J. Steyaert, and W. Sansen, “A 10-bit 1-GSample/s Nyquist current-steering CMOS D/A converter,” IEEE J. Solid-State Circuits, vol. 36, pp. 315-324, Mar. 2001.

[26] T. H. Kuo, K. D. Chen, and H. R. Yeng, “A wideband CMOS sigma-delta modulator with incremental data weighted averaging,” IEEE J. Solid-State Circuits, vol. 37, pp. 11-17, Jan. 2002.

[27] D. Johns and K. Martin, Analog Integrated Circuit, Wiley, 1997.

[28] K. W. Martin, “Complex signal processing is not complex,” IEEE Trans. Circuits Syst, vol. 51, no. 9, pp. 1823–1836, Sep. 2004.

[29] James Candy, “Decimation for Sigma-Delta Modulation,” IEEE Transaction on Communications, Vol. COM-34, pp. 72-26, Jan. 1986.

[30] Brian Brandt, Oversampled Analog-to-Digital Conversion, Ph.D. Dissertation, Stanford University, 1991.

[31] S. A. Jantzi, Quadrature Bandpass Delta-Sigma Modulation for Digital Radio, Ph.D. Dissertation, University of Toronto, 1997.

[32] R. E. Crochiere and L. R. Rabiner, Multirate Digital Signal Processing, Prentice Hall,1983.
[33] B. P. Brandt and B. A. Wooley, “A Low-Power, Area-Efficient Digital Filter for Decimation and Interpolation,” IEEE J. Solid-State Circuits, vol. 29, no. 6, pp. 679-687, June. 1994.

[34] M. T. Heath , Scientific Computing: An Introductory Survey, McGraw-Hill, 2002.

[35] N. H. E. Weste and D. Harris, CMOS VLSI Design- A Circuits and Systems Perspective, 3rd edition, Addison Wisley, NY, 2005.

[36] L. Wanhammar and H. Johansson. Digital Filters. LiU-Tryck, 2007.

[37] L. Cederstrom, Power Efficient Digital Decimation Filters for ΣΔ ADCs, M.S thesis, Linkoping University, 2009.

[38] I. Koren, Computer Arithmetic Algorithms: Second Edition, CRC Press, 2001.

[39] F. Chen, S. Ramaswamy, and B. Bakkaloglu, “A 1.5V 1mA 80dB passive ΣΔ ADC in 0.13μm digital CMOS process,” ISSCC Dig. Tech. Papers , 2003, pp. 496–497.

[40] F. Chen and B. Leung, “A 0.25mW low-pass passive sigma-delta modulator with build-in mixer for a 10-MHz IF input,” IEEE J. Solid-State Circuits, vol. 32, no. 6, pp. 774–782, Jun. 1997.

[41] T. Song, Z. Cao, and S. Yan, " A 2.7-mW 2-MHz continuous-time delta sigma modulator with a hybrid active-passive loop filter," IEEE J. Solid-State Circuits, vol. 43, no. 2, pp. 330-341, Feb. 2008.

[42] R. Zanbaghi and T.S. Fiez, “A novel low power hybrid loop filter for continuous-tme Sigma-Delta modulators.” In Proc. of IEEE ISCAS, pp. 3114-3117, May 2009.

[43] L. J. Breems, E. J. van der Zwan, and J. H. Huijsing, “A 1.8-mW CMOS modulator with integrated mixer for A/D conversion of IF signals,” IEEE J. Solid-State Circuits, vol. 35, pp. 468–475, Apr. 2000.

[44] J. A. Cherry and W. M. Snelgrove, “Clock Jitter and Quantizer Metastability in Continuous-Time Delta–Sigma Modulators,” IEEE Trans. Circuits Syst. II, vol. 46, No. 9, pp. 661-676, June. 1999.

[45] S. W. Huang, Z. Y. Chen, C. C. Hung, and C. M. Chen, “A Fourth-Order FeedForward Continuous-Time Delta-Sigma ADC with 3MHz Bandwidth,” In Proc. of IEEE MWSCAS, pp. 33-36, Aug. 2010.

[46] M. C. Huang and S. I. Lu, “A fully differential comparator-based switched-capacitor ΔΣ modulator,” IEEE Trans. Circuits Syst. II, vol. 56, pp. 369–373, May 2009.