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研究生:張書維
研究生(外文):SHU-WEI CHANG
論文名稱:適用於軟體無線電之類比基頻電路
論文名稱(外文):Analog baseband for software-defined radio application
指導教授:陳筱青陳筱青引用關係
指導教授(外文):Hsiao-Chin Chen
學位類別:碩士
校院名稱:國立臺灣科技大學
系所名稱:電機工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2010
畢業學年度:99
語文別:中文
論文頁數:106
中文關鍵詞:軟體定義無線電複數型帶通濾波器自動校正迴路反混疊失真濾波器低中頻接收機直接轉換接收機
外文關鍵詞:Software Defined Radiocomplex bandpass filterautomatic tuning loopanti-aliasing filterLow-IF receiverdirect-conversion receiver
相關次數:
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本論文使用UMC90nm 1P9M CMOS製程,設計了適用於GSM、IEEE 802.15、W-CDMA、IEEE802.11a/b/g及IEEE802.16a無線通訊技術的複數型帶通濾波器及其自動校正電路,與適用於GSM、W-CDMA無線通訊技術的反混疊失真濾波器。複數型帶通濾波器與反混疊失真濾波器,分別應用於低中頻接收機架構及直接轉換接收機架構。可應用於軟體定義無線電(Software Defined Radio, SDR) 接收機中,透過改變軟體使系統應用於不同的無線通訊標準。
複數型帶通濾波器採用轉導電容式濾波器實現,並利用改變電容陣列值改變濾波器的頻寬,使其應用於不同的無線通訊系統,頻寬範圍為153.1KHz~1.53MHz(低頻模式)、4.28MHz~70.9MHz(高頻模式)。低頻模式與高頻模式消耗功率分別為2.61mW、10.17mW,晶片面積為1.99mm2 (1.53mm×1.3mm)。自動校正迴路用於降低製程變異對於主動式濾波器頻率精確度的影響。調整方式使用主僕式架構,利用逐次逼近的方式調整濾波器的電容陣列值以達到校正效果。自動校正電路整體消耗功率為2.45mW,晶片佈局面積為0.8mm2 (0.615mm×1.3mm)。反混疊失真濾波器包含了轉導電容式濾波器以及縮減取樣濾波器,可降低鄰近通道以及距離很遠的通道干擾。反混疊失真濾波器整體消耗功率為2.74mW,晶片面積為1.12mm2 (1.02mm×1.17mm)。
This thesis presents the design and implements an adjustable complex bandpass filter with its automatic tuning loop circuit for GSM, IEEE 802.15, W-CDMA, IEEE802.11a/b/g and IEEE802.16a wireless communication standards ,and an anti-aliasing filter for GSM, W-CDMA wireless communication standards in UMC90nm 9-metal-single-poly CMOS process. The complex bandpass filter and the anti-aliasing filter are used in the Low-IF receiver architecture and the direct-conversion receiver architecture, respectively. Both filters can be used in Software Defined Radio (SDR) receivers, and operate in variety of wireless communication standards.
The complex bandpass filter is based on transconductor-C integrators, and changing bandwidth by different cap array values of filter to operate in various wireless communication systems. There are two operating modes in the complex bandpass filter where the -3dB bandwidths range from 153.1 KHz to 1.53 MHz (low frequency mode) and from 4.28 MHz to 70.9 MHz (high frequency mode). The power consumption of low frequency mode and high frequency mode are 2.61mW and 10.17mW, respectively, and the chip area is 1.99mm2(1.53mm×1.3mm). Automatic tuning loop is used for decrease the inaccuracy of the active filter bandwidth due to process variation. Tuning method is implemented in the master-slave architecture, and the cap array values of filter are determined by Successive Approximations method to self-calibrate the bandwidth of complex band filter. The power consumption of automatic tuning loop circuit is 2.45mW, and the chip area is 0.8mm2 (0.615mm×1.3mm).The anti-aliasing filter consists a transconductor-C filter and a decimation filter. It can suppress interference from adjacent channel and remote channel. The power consumption of anti-aliasing filter is 2.74mW, and the chip area is 1.12mm2 ( 1.02mm×1.17mm ).
摘要 i
Abstract iii
誌謝 v
目錄 vii
圖目錄 xi
表目錄 xv
第一章 緒論 1
1.1 研究動機 1
1.2 章節概要 5
參考文獻 6
第二章 可調式複數型帶通濾波器 7
2.1 電路架構 9
2.1.1 轉導放大器 9
2.1.2 低通濾波器 12
2.1.3 複數型帶通濾波器 14
2.2 模擬結果 16
2.2.1 低通濾波器模擬 17
2.2.2 複數型帶通濾波器模擬 17
2.3規格表 20
2.4 晶片佈局 22
2.5 量測 23
2.5.1 量測環境 24
2.5.2 量測結果 26
2.5.3 討論 28
參考文獻 29
第三章 自動校正迴路 31
3.1 電路架構 34
3.1.1 除四除頻器 34
3.1.2 主濾波器(低通濾波器) 35
3.1.3 相位頻率偵測器、電荷幫浦 39
3.1.4 電壓比較器 41
3.1.5 逐次逼近暫存器 42
3.1.6 時序控制器 44
3.2 自動校正迴路模擬結果 45
3.2.1 低頻帶模式模擬結果 (MODE 0) 45
3.2.2 高頻帶模式模擬結果 (MODE 1) 52
3.3 規格表 56
3.4 晶片佈局 58
參考文獻 60
第四章 反混疊失真濾波器 61
4.1取樣器 62
4.2 窗口式積分取樣器 62
4.2.1 取樣頻率的選擇 65
4.2.2 縮減取樣濾波器 68
4.3 模擬結果 72
4.4 晶片佈局 75
4.5量測 76
4.5.1 量測環境 76
4.5.2 量測結果 78
4.5.3 討論 79
參考文獻 81
第五章 總結與未來展望 83
5.1總結 83
5.2未來展望 83
作者簡介 85
ch1:
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ch2:
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ch3:
[1]H. Kondo et al., “Complex BPF for Low-IF Receivers with an Automatic Digital tuning Circuit,” IEEE Radio Frequency Integrated Technology Symposium, pp.74-77, 2007.
[2]H. Yamazaki, K.Oishi, and K. Gotoh, “An Accurate Center Frequency Tuning Scheme for 450-kHz CMOS Gm-C Bandpass Filters,” IEEE J. Solid-State Circuits, vol. 34, pp. 1691-1697, Dec. 1999.
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ch4:
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[2]J. Yuan, “A charge sampling mixer with embedded filter function for wireless applications,” in Proc. 2nd Int. Conf. Microwave and Millimeter Wave Technology, Beijing, China, 2000, pp. 315–318.
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[4]R. Bagheri et al., “Software-defined Radio Receiver: Dream to Reality,” IEEE Commun. Mag., vol. 44, no. 8, pp. 111–118, Aug. 2006.
[5]R. Bagheri et al., "An 800-MHz-6-GHz software-defined wireless receiver in 90 nm CMOS," IEEE J. Solid-State Circuits, vol. 41, no. 12, Dec. 2006.
[6]A. Mirzaei et al., “Analysis of First-order Anti-aliasing Integration Sampler,” IEEE Trans. Circuits Syst. I, vol. 55, no. 10, pp. 2994–3005, Nov. 2008.
[7]A. Mirzaei et al., "A second-order anti-aliasing prefilter for an SDR receiver," in Proc. IEEE Custom Integr. Circuits Conf., Sep. 18-21, 2005, pp. 629-632.
[8]A. A. Abidi, “The Path to the Software-Defined Radio Receiver,” IEEE J. Solid-State Circuits, vol. 42, no. 5, May 2007.
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