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研究生:郭亘倫
研究生(外文):Kuo, Hsuan-Lun
論文名稱:參考電壓電路與鎖相迴路電路 研究與實現
論文名稱(外文):A Study and Implementation of Referenced Circuit And Phase Locked Loop Circuit
指導教授:陳宏偉陳宏偉引用關係
指導教授(外文):Chen, Hung-Wei
口試委員:顏文正盧志文陳宏偉
口試委員(外文):Yen, Wen-ChengLu, Chih-WenChen, Hung-Wei
口試日期:2011-06-25
學位類別:碩士
校院名稱:國立聯合大學
系所名稱:電子工程學系碩士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2011
畢業學年度:99
語文別:英文
論文頁數:116
中文關鍵詞:能隙參考電壓電路次能隙參考電壓電路溫度補償低供給電壓低功率鎖相迴路雙倍頻器
外文關鍵詞:bandgap referencesubbandgap referencetemperature-compensationlow supply voltagelow powerphase locked loopfrequency doubler
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在本篇論文中,我們將提出兩種型式的能隙電壓參考電路。這兩種型式的能隙電壓參考電路分別為”使用三種電壓補償電路組成的低供給電壓次能隙參考電壓電路”以及”運用電流差動放大器與動態導通電壓金氧半電晶體構成低供給電壓金氧半電晶體參考電壓電路”。 在”使用三種電壓補償電路組成的低供給電壓次能隙參考電壓電路”中使用差動放大器輸出正溫度係數電壓,使用二極體接法的雙載子接面電晶體、二極體接法的N型金氧半電晶體、以及二極體接法的P型金氧半電晶體輸出負溫度係數電壓。在”運用電流差動放大器與動態導通電壓金氧半電晶體構成低供給電壓金氧半電晶體參考電壓電路”中運用電流式差動放大器以及動態導通電壓金氧半電晶體來達成溫度抵補。第一個電路使用標準的台積電0.18微米互補式金氧半製程實現。第二個電路使用標準的台積電0.35微米互補式金氧半製程實現。

我們也嘗試設計了兩個鎖相迴路電路,分別是使用了電感與電容共振槽電壓控制震盪器以及環型電壓控制震盪器兩種結構。兩種鎖相迴路電路接使用了雙倍頻器。第一種電路使用標準的台積電0.18微米互補式金氧半製程實現。第二個電路使用標準的台積電0.35微米互補式金氧半製程實現。
In this thesis, we will suppose two types of band-gap reference circuit. These two types of band-gap reference circuit are ―A Low Supply Voltage Temperature-Compensation CMOS Sub-band-gap Reference with three Averaging Circuitry‖, and ―A low power supply CMOS band-gap reference voltage generator used current differential amplifier and DTMOST diode‖. The ―A Low Supply Voltage Temperature-Compensation CMOS Sub-band-gap Reference with three Averaging Circuitry‖ is used differential amplifier to produce the positive temperature coefficient voltage and used diode-connected bipolar junction transistor (BJT), diode-connected N-type Metal Oxide Semiconductor, and diode-connected P-type Metal Oxide Semiconductor to produce the negative temperature coefficient voltage. The circuit ―A low power supply CMOS band-gap reference voltage generator used current differential amplifier and DTMOST diode‖ is used a current amplifier and DTMOST diode to achieve the temperature cancellation. The first circuit is implemented in a standard 0.18um TSMC CMOS process. The second circuit is implemented in a standard 0.35um TSMC CMOS process.

And we tried to design the Phase Locked Loop circuit with LC-tank VCO and ring oscillator VCO. Both of them are used the frequency doubler. The first circuit is implemented in a standard 0.18um TSMC CMOS process. The second circuit is implemented in a standard 0.35um TSMC CMOS process.
Acknowledgments ...................................................................................................................... I
中文摘要 .............................................................................................................................. II
Abstract ............................................................................................................................. III
TABLE OF CONTENTS .................................................................................................................... IV
List of Figures ...................................................................................................................... VII
List of Tables ....................................................................................................................... X

Chapter 1. Introduction .............................................................................................................. 1
1.1. Motivation for the Research ..................................................................................................... 1
1.2. Structure of the Thesis ......................................................................................................... 2

Chapter 2. The Theorem of Band-gap Reference ......................................................................................... 3
2.1. Negative Temperature Coefficient Voltage ........................................................................................ 3
2.2. Positive Temperature Coefficient Voltage ........................................................................................ 4
2.3. Conventional Band-gap referenced circuit ........................................................................................ 5

Chapter 3. A Low Supply Voltage Temperature-Compensation CMOS Sub-band-gap Reference with Three Averaging Circuitry ...................8
3.1. Introduction .................................................................................................................... 9
3.2. Proposed Sub-band-gap Reference Voltage Circuit.................................................................................. 9
3.2.1. Averaging Circuitry ........................................................................................................... 11
3.2.2. Differential Amplifier ........................................................................................................ 14
3.2.3. Beta-Multiplier Reference with Start-up Technique ............................................................................. 15
3.3. Verification .................................................................................................................... 16
3.3.1. Simulation .................................................................................................................... 17
3.3.2. Measurement ................................................................................................................... 19

Chapter 4. A low power supply CMOS band-gap reference voltage generator used current differential amplifier and DTMOST diode ......... 22
4.1. Introduction .................................................................................................................... 22
4.2. The Conventional Band-gap Reference Circuit and the Conventional Supply-Independent Biasing Circuit with Start-Up circuit ....... 23
4.3. -Proposed Band-gap Voltage Reference ............................................................................................ 27
4.4. Simulation and Measurements Results ............................................................................................. 33
4.5. Conclusion ...................................................................................................................... 35

Chapter 5. The Theorem of Phase Locked Loop .......................................................................................... 39
5.1. Basic Concepts .................................................................................................................. 39
5.1.1. VCO Dynamics .................................................................................................................. 39
5.1.2. Phase Detector ................................................................................................................ 40
5.2. Voltage Control Oscillators ..................................................................................................... 42
5.2.1. General Considerations ........................................................................................................ 42
5.2.2. Basic LC Oscillator Topologies ................................................................................................ 44
5.2.3. One-Port View ................................................................................................................. 47
5.2.4. Ring Oscillators .............................................................................................................. 48
5.2.5. Amplitude Limiting ............................................................................................................ 52
5.2.6. VOLTAGE-CONTROLLED OSCILLATORS ................................................................................................ 55
5.3. Basic PLL ....................................................................................................................... 56
5.3.1. Simple Loop ................................................................................................................... 56
5.3.2. Loop Dynamics in Locked State ................................................................................................. 58
5.4. Charge Pump PLLs ................................................................................................................ 62
5.4.1. Phase/Frequency Detectors ..................................................................................................... 62
5.4.2. Charge Pumps .................................................................................................................. 64
5.4.3. Charge Pumps PLLs ............................................................................................................. 65
5.5. Type I and Type II PLLs ......................................................................................................... 68
5.6. Frequency Multiplication and Synthesis .......................................................................................... 69
5.6.1. Frequency Multiplication ...................................................................................................... 69
5.6.2. Frequency Synthesis ........................................................................................................... 71
5.7. FREQUENCY DIVIDERS .............................................................................................................. 71
5.7.1. Divide-by-Two Circuits ........................................................................................................ 72
5.7.2. Dual-Modulus Dividers ......................................................................................................... 75

Chapter 6. An Implementation of 10GHz Phase Locked Loop Circuit ...................................................................... 79
6.1. Introduction .................................................................................................................... 79
6.2. Proposed Phase Locked Loop Circuit .............................................................................................. 80
6.2.1. QVCO and Frequency Doubler .................................................................................................... 81
6.2.2. Frequency Divider ............................................................................................................. 82
6.2.3. Phase Frequency Detector ...................................................................................................... 83
6.2.4. Voltage Pump, Charge Pump, and Low Pass Filter ................................................................................ 84
6.3. Experiment Simulation Result .................................................................................................... 86
6.4. Conclusion ...................................................................................................................... 88

Chapter 7. 2.4GHz Phase Locked Loop using Ring Oscillator QVCO and Frequency Doubler ................................................. 89
7.1. Introduction .................................................................................................................... 89
7.2. Proposed Frequency Synthesizer .................................................................................................. 90
7.2.1. Delay cell and QVCO ........................................................................................................... 91
7.2.2. Frequency Doubler ............................................................................................................. 93
7.3. Experiment Simulation Result .................................................................................................... 94
7.4. Conclusion ...................................................................................................................... 96

Chapter 8. Future Work ............................................................................................................... 98

References ........................................................................................................................... 99
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