臺灣博碩士論文加值系統

脈衝產生器是一種廣泛應用的電路模組，尤其是運用在脈衝觸發正反器與通訊系統中。脈衝觸發正反器設計，與傳統的主僕式正反器相比，脈衝觸發正反器由於其電路複雜性低，可以降低系統約30％的功率消耗；而在通訊系統設計，由於脈衝訊號具有較佳的穿透力，非常適合做為室內短距離通訊，其調變方法可使用脈衝振幅調變（PAM）及脈衝位置調變（PPM）。
本論文提出五種可調式脈衝產生器電路，其架構為利用NAND邏輯閘的輸入端連接一延遲電路，透過可調整電流電路的不同充/放電電流來調整延遲信號，藉以產生可改變脈衝寬度的脈衝產生器；所提出的電路具有電路簡單、脈波寬度可調整，以及平均消耗功率較少之優點。
本論文提出之電路經由HSPICE電路模擬軟體模擬，在使用TSMC N-Well 0.35um 2P4M的製程參數下，可以證實本論文之電路設計理論的正確性，本論文之電路亦可使用在數位電路系統中。在五種電路中，當訊號輸入頻率為50MHz及供應電壓為3.3v時，最大之輸出脈衝寬度為3800ps，最小之輸出脈衝寬度為350ps，平均消耗功率皆低於200mW。

The impulse generators are the widely used circuit modules. Especially applied in the impulse triggered flip-flops and the communication systems. In the impulse triggered flip-flops design, as compared to the traditional master-slave flip-flops, the impulse triggered flip-flops can reduce system power consumption about 30% due to its low complexity. In the communication system design, the impulse signal has a relatively good penetration and suitable for a short-range of the indoor communications. The modulation method can be the pulse amplitude modulation (PAM) and the pulse position modulation (PPM).
In this thesis, five adjustable impulse generator circuits have been proposed. The structure of the circuit is a NAND gate with a delay circuit at its input. By adjusting the circuit’s charging / discharging current through the NAND gate, the delay time of the signal can be adjusted. Consequently, the impulse width can be changed. This proposed circuit featured with simple circuit architecture, adjustable impulse width, and lower power consumption.
All the proposed circuits have been simulated with HSPICE circuit simulation software and the TSMC N-Well 0.35um 2P4M process parameters were used. Simulation results are given to confirm the validity of the theory analysis. These circuits can also be used in digital circuit systems. When the frequency is 50MHz and the supply voltage is 3.3v, the maximum output impulse width is 3800ps while the smallest width is 350ps. Moreover the average power consumptions are all less than 200mW.

中文摘要 i
英文摘要 iii
誌謝 v
目錄 vi
表目錄 x
圖目錄 xi
符號說明 xiv
第一章　緒論 1
1.1　研究動機與目的 1
1.2　文獻回顧 2
1.3　研究重點與特色 3
1.4　內容章節 4
第二章　脈衝產生器現有技術 5
2.1　傳統式脈衝產生器 7
2.2　改良式脈衝產生器 8
第三章　可調整脈衝寬度之脈衝產生器設計 12
3.1　利用可調整轉換電壓之史密特觸發器所實現之可調式脈衝產生器 12
3.1.1　電路架構及工作原理 13
3.1.2　低電壓且快速之史密特觸發器 15
3.2　利用可調整電流之反相器所實現之可調式脈衝產生器 17
3.2.1　電路架構及工作原理 18
3.3　利用可調式史密特觸發器所實現之可調式脈衝產生器 20
3.3.1　電路架構及工作原理 20
3.3.2　CMOS可調式史密特觸發器 22
3.4　利用延遲元件所實現之可調式脈衝產生器 26
3.4.1　電路架構及工作原理 26
3.4.2　類比電路之延遲元件（DCE） 28
3.5　利用新型延遲線所實現之可調式脈衝產生器 28
3.5.1　電路架構及工作原理 29
3.5.2　新型延遲線架構 30
第四章　模擬與量測 33
4.1　設計流程 33
4.2　電路模擬結果 35
4.2.1　利用可調整轉換電壓之史密特觸發器所實現之可調式脈衝產生器 36
4.2.2　利用可調整電流之反相器所實現之可調式脈衝產生器 39
4.2.3　利用可調式史密特觸發器所實現之可調式脈衝產生器 41
4.2.4　利用延遲元件所實現之可調式脈衝產生器 44
4.2.5　利用新型延遲線所實現之可調式脈衝產生器 47
4.2.6　可調式脈衝產生器之脈衝寬度大小比較 50
4.3　晶片實現與佈局後模擬結果 51
4.3.1　利用可調整電流之反相器所實現之可調式脈衝產生器 51
4.3.2　量測方法與測試儀器 53
4.3.3　量測結果 53
第五章　結論 56
參考文獻 57
英文論文大綱 59
簡歷(CV) 62

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