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[1]Yuan-Wen Hsiao, Member, IEEE, and Ming-Dou Ker, Fellow, IEEE “A 5-GHz Differential Low-Noise Amplifier With High Pin-to-Pin ESD Robustness in a 130-nm CMOS Process” in IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 57, NO. 5, MAY 2009, pp. 1044~1053 [2]Albert Z. H. Wang, Senior Member, IEEE, Haigang Feng, Student Member, IEEE, Rouying Zhan, Student Member, IEEE, Haolu Xie, Guang Chen, Qiong Wu, Xiaokang Guan, hihua Wang, Senior Member, IEEE, and Chun Zhang “A Review on RF ESD Protection Design” in IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 52, NO. 7, JULY 2005, pp.1304~1311 [3]X. Wang, H. Tang, L. Lin, Q. Fang, H. Zhao, Albert Wang, Fellow, IEEE, G. Zhang, X. Wang, Y Zhou, Lee Yang and H. Chen “ESD Protection for RF/AMS ICs: Design and Optimization” in 2009 IEEE [4]Yiqun Cao, Ulrich Glaser, Stephan Frei and Matthias Stecher “A Failure Levels Study of Non-Snapback ESD Devices for Automotive Applications” in IRPS10 , pp.4D.1.1~ 4D.1.8 [5]Peter Glattli, Swiss Telecom PTT, R&D, Head of Electrostatics “What is a real 1 GHz bandwidth ESD generator calibration” in EOSIESD SYMPOSIUM 96-180, pp.4.2.1~4.2.6 [6]Albert Wang “Recent Developments in ESD Protection For RF ICs” in 2003 IEEE, pp.171~178 [7]Madhur Bobde, Shekar Mallikarjunaswamy, Moses Ho, Francois Hebert Alpha & Omega Semiconductor “A Novel ESD Super-Clamp Structure for TVS Applications” in 2008 IEEE, pp.897~900 [8]Chris Moore “A Comparison of Quasi-Static Characteristics and Failure Signatures of GMR Heads subjected to CDM and HBM ESD Events” in EOSIESD SYMPOSIUM 00-34, pp.3B.6.1~3B.6.6 [9]Ke Gong, Member, IEEE, Haigang Feng, Student Member, IEEE, Rouying Zhan, and Albert Z. H. Wang, Senior Member, IEEE “A Study of Parasitic Effects of ESD Protection on RF ICs” in IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 50, NO. 1, JANUARY 2002, pp.393~402 [10]R.Y.Zhan, H.G.Feng, Q.Wu, G.Chen, XKGuan and AlberLZWang Dept. of Electrical & Computer Engineering, Illinois Institute of Technology “A Technology-independent CAD Tool For ESD Protection Device Extraction – ESDExtractor” in 2002 IEEE, pp.510~513 [11]Louis Luh, John Choma, Jr., Jeffrey Draper “A Zener-Diode-Activ ated ESD Pmtection Circuit for Sub-Micron CMOS Process” in 2000 IEEE, pp.V-65~V-68 [12]Hsiang-Pin Hung, Ming-Dou Ker, Shih-Hung Chen, and Che-Hao Chuang “Abnormal ESD Damages Occur in Interface Circuits between Different Power Domains in ND-Mode MM ESD Stress” in 2006 IEEE, pp.163~166 [13]Shih-Hung Chen, Ming-Dou Ker, Fellow, IEEE, and Hsiang-Pin Hung “Active ESD Protection Design for Interface Circuits Between Separated Power Domains Against Cross-Power-Domain ESD Stresses” in IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 8, NO. 3, SEPTEMBER 2008, pp.549~560 [14]Chuah Cheow Theng, Yip Boon Chuan, Prof Dr Othman Sidek (USM) “An Automated Tool Deployment for ESD(Electro-Static-Discharge) Correct-by-Construction Strategy in 90 nm Process” in ICSE2004 Proc. 2004, Kuala Lumpur, Malaysia, pp.61~67 [15]Shih-Hung Chen and Ming-Dou Ker, Fellow, IEEE “Area-Efficient ESD-Transient Detection Circuit With Smaller Capacitance for On-Chip Power-Rail ESD Protection in CMOS ICs” in IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 56, NO. 5, MAY 2009, pp.359~363 [16]Chih-Ting Yeh and Ming-Dou Ker, Fellow, IEEE “Capacitor-Less Design of Power-Rail ESD Clamp Circuit With Adjustable Holding Voltage for On-Chip ESD Protection” in IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 11, NOVEMBER 2010, pp.2476~2486 [17]Chuah Cheow Theng, Prof Dr Othman Sidek (USM) “Clamp Placement Optimization in Full-Chip ESD (Electro-Static-Discharge) Design” in IEMT 20061, Putrajaya, Malaysia, pp.202~206 [18]Mansun Chan, Selina S. Yuen, Zhi-Jian Ma, Kelvin Y. Hui, Ping K. KO and Chenming Hu “Comparison of ESD Protection Capability of SOI and BULK CMOS Output Buffers” in 1994 IEEEIIRPS, pp.292~298 [19]Ming-Dou Ker, Senior Member, IEEE, and Bing-Jye Kuo, Student Member, IEEE “Decreasing-Size Distributed ESD Protection Scheme for Broad-Band RF Circuits” in IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 53, NO. 2, FEBRUARY 2005, pp.582~589 [20]Ming-Dou Ker, Senior Member, IEEE, and Kun-Hsien Lin, Student Member, IEEE “Design on ESD Protection Scheme for IC With Power-Down-Mode Operation” in IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 8, AUGUST 2004, pp.1378~1382 [21]Jian Liu, L. Lin1, X. Wang1, Z. Shi1, S. Fan, H. Tang1, A. Wang1, Y. Cheng and B. Zhao,Dept. of Electrical Engineering, University of California, Riverside, CA, “Design Optimization of Adjustable Triggering Dual-Polarity ESD Protection Structures” in 2010 IEEE, pp.149~152 [22]Howard H. Nick, Brock E. Osborn, Chang Y. Wu “DIAGNOSTIC EFFECTJVENESS IN COMPUTER SYSTEMS USING DETERMINISTIC RANDOM ESD” in 1990 IEEE, pp.274~279 [23]Matthew N. O. Sadiku and Cajetan M. Akujuobi “Electrostatic discharge (ESD) ”in DECEMBER 2003/JANUARY 2004, 2003 IEEE, pp.39~41 [24]Steven H. Voldman “Electrostatic Discharge (ESD) and Technology Scaling - The Future of ESD Protection in Advanced Technology” in 2008 IEEE [25]THIET THE LA1 “Electrostatic Discharge (ESD) Sensitivity of Thin-Film Hybrid Passive Components” in IEEE TRANSACTIONS ON COMPONENTS, HYBRIDS, AND MANUFACTURING TECHNOLOGY, VOL. 12, NO. 4, DECEMBER 1989, pp.627~638 [26]Ming-Dou Ker, Hsin-Chyh Hsu, and Jeng-Jie Peng “Electrostatic Discharge Implantation to Improve Machine-Model ESD Robustness of Stacked NMOS in Mixed-Voltage I/O Interface Circuits” in Proceedings of the Fourth International Symposium on Quality Electronic Design (ISQED’03) [27]Ming-Dou Ker, hhn-Hsien Chang, and Tung-Yang Chen “ESD BUSES FOR WHOLE-CHIP ESD PROTECTION” in 1999 IEEE, pp.I-545~I-548 [28]A1 Wallash “ESD CHALLENGES IN MAGNETICRE CORDING: PAST, PRESENT AND FUTURE” in IEEE 03CH37400. 41sl Annual lntemalional Reliability Physics Symposium, Dallas, Texas, 2003, pp.222~228 [29]Yintat Ma, Member, IEEE, and G. P. Li “ESD Protection Design Considerations for InGap/GaAs HBT RF Power Amplifiers” in IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 53, NO. 1, JANUARY 2005, pp.221~228 [30]Ming-Dou Ker, Wen-Yu Lo, Chien-Ming Lee, Chia-Pei Chen, and Hong-Sing Kao “ESD Protection Design for 900-MHz RF Receiver with 8-kV HBM ESD Robustness” in 2002 IEEE Radio Frequency Integrated Circuits Symposium, pp.427~430 [31]Ming-Dou Ker and Bing-Jye Kuo “ESD Protection Design for Broadband RF Circuits With Decreasing-Size Distributed Protection Scheme” in 2004 IEEE Radio Frequency Integrated Circuits Symposium, pp.383~386 [32]Ming-Dou Ker and Che-Hao Chuang “ESD Protection Design for High-Speed I/O Interface of Stub Series Terminated Logic (SSTL) in a 0.25-um Salicided CMOS Process” in Proceedings of I l l h IPFA 2004, Taiwan, pp.217~220 [33]Ming-Dou Ker and Kun-Hsien Lin “ESD PROTECTION DESIGN FOR IC WITH POWER-DOWN-MODE OPERATION” in ISCAS 2004, pp.II-717~II-720 [34]Ming-Dou Ker, Senior Member, IEEE, Chyh-Yih Chang, Member, IEEE, and Yi-Shu Chang “ESD Protection Design to Overcome Internal Damage on Interface Circuits of a CMOS IC With Multiple Separated Power Pins” in IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES, VOL. 27, NO. 3, SEPTEMBER 2004, pp.445~451 [35]Ming-Dou Ker, Fellow, IEEE, and Wei-Jen Chang, Member, IEEE “ESD Protection Design With On-Chip ESD Bus and High-Voltage-Tolerant ESD Clamp Circuit for Mixed-Voltage I/O Buffers” in IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 55, NO. 6, JUNE 2008, pp.1409~1416 [36]Harald Gossner “ESD protection for the deep sub micron regime – a challenge for design methodology” in Proceedings of the 17th International Conference on VLSI Design (VLSID’04) [37]Albert Wallash “ESD Testing of Head Stack Assemblies Used in Magnetic Recording Hard Disk Drives” in EOS/ESD SYMPOSIUM 99-297, pp. 3C.2.1~3C.2.5 [38]Rouying Zhan, Haigang Feng, Student Member, IEEE, Qiong Wu, Haolu Xie, Xiaokang Guan, Guang Chen, and Albert Z. H. Wang, Senior Member, IEEE “ESDInspector - A New Layout-Level ESD Protection Circuitry Design Verification Tool Using a Smart-Parametric Checking Mechanism” in IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 23, NO. 10, OCTOBER 2004, pp.1421~1428 [39]Guang Chen and Albert Wang “Evaluating RF ESD Protection Design: An Overview” in Proceedings of I S h IPFA 2004, Taiwan, pp.205~208 [40]Ming-Dou Ker, Jeng-Jie Peng, and Hsin-Chin Jiang “Failure Analysis of ESD Damage in a High-Voltage Driver IC and the Effective ESD Protection Solution” in Proceedings 491h IPFA 2002, Singapore, pp.84~89 [41]Cheng-Cheng Yen and Ming-Dou Ker “FAILURE OF ON-CHIP POWER-RAIL ESD CLAMP CIRCUITS DURING SYSTEM-LEVEL ESD TEST” in IEEE 07CH37867 45th Annual International Reliability Physics Symposium, Phoenix, 2007, pp.598~599 [42]Ming-Dou Ker and Yu-Yu Sung “Hardware/Firmware CO-Design in an 8-Bits Microcontroller to Solve the System-Level ESD Issue on Keyboard” in EOS/ESD SYMPOSIUM 99-352, pp.4A.5.1~4A.5.9 [43]Ming-Dou Ker, Fellow, IEEE, and Chun-Yu Lin, Member, IEEE “High-Voltage-Tolerant ESD Clamp Circuit With Low Standby Leakage in Nanoscle CMOS Process” in IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 7, JULY 2010, pp.1636~1641 [44]SHIAN AUR, MEMBERI,E EE, AMITAVA CHATTERJEE, MEMBERI,E EE,A ND THOMAS POLGREEN “Hot-Electron Reliability and ESD Latent Damage” in IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 35. NO. 12, DECEMBER 1988, pp.2189~2193 [45]Joachim C. Reiner, Thomas Keller, Hans Jaggi, Silvio Mira “Impact of ESD-induced soft drain junction damage on CMOS product lifetime” in Proceedings of 8"' IPFA 2001, Singapore, pp.77~78 [46]Ming-Dou Ker, Fellow, IEEE, and Cheng-Cheng Yen, Student Member, IEEE “Investigation and Design of On-Chip Power-Rail ESD Clamp Circuits Without Suffering Latchup-Like Failure During System-Level ESD Test” in IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 11, NOVEMBER 2008, pp.2533~2545 [47]Ber-Chin Yap, Charles R. Patton “Investigation of ESD Transient EMI Causing Spurious Clock Track Read Transitions During Servo-Write” in EOS/ESD SYMPOSIUM 00-233, pp. 2c.11.1~2c.11.6 [48]Randy Bordeos, Zhang Lianzhu, Silas T.F. Hung and C.Y. Wong “Investigation of GMR Sensor Microstructural Changes Induced by HBM ESD Using Aadvanced Microscopy Approach” in EOS/ESD SYMPOSIUM 00-485, pp. 4B.4.1~4B.4.6 [49]Ming-Dou Ker, Fellow, IEEE, and Yuan-Wen Hsiao, Member, IEEE “Investigation on Board-Level CDM ESD Issue in IC Products” in IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 8, NO. 4, DECEMBER 2008, pp.694~704 [50]Albcrt Mng. H. Feng. G Chen. R. Zhan. H. Xie. Q. Wu and X. Guan “Key Aspects on ESD Protection Design for ICs Mixed-Mode Simulation and RF/Mixed-Signal ESD” in IEEE 2003, pp.1000~1005 [51]Sheng-Huei Dai, Chrong-Jung Lin, and Ya-Chin King “LOW VOLTAGE TRANSIENT VOLTAGE SUPPRESSOR WITH V-GROOVE STRUCTURE” in IEEE CFP08RPS-CDR 46th Annual International Reliability Physics Symposium, Phoenix, 2008, pp.278~282 [52]J. Urresti, S. Hidalgo, D. Flores, J. Roig, J. Rebollo, J.MillBn “LOW VOLTAGE TVS DEVICES: DESIGN AND FABRICATION” in 2002 IEEE, pp.257~260 [53]Nitin Mohan and Anil Kumar “Modeling ESD protection” in FEBRUARY/MARCH 2005, 2005 IEEE, pp.21~24 [54]H. Hyatt, J,. Harris, J. Colby and P. Belled “Optimizing The Performance of ESD Circuit Protection Devices” in EOS/ESD SYMPOSIUM 0041, pp.1B.1.1~1B.1.7 [55]R. Kenneth Keenan , Leonard A. Rosi “SOME FUNDAMENTAL ASPECTS OF ESD TESTING” in 1991 IEEE, pp.236~241 [56]Ming-Dou Ker, Senior Member, IEEE, and Tung-Yang Chen, Member, IEEE “Substrate-Triggered ESD Protection Circuit Without Extra Process Modification” in IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 2, FEBRUARY 2003, pp. 295~302 [57]Kai Wang, Dr. Pornmerenke, Jian Min,Zhang, Ramachandran Chundru “The PCB level ESD immunity study by using 3 Dimension ESD Scan System” in IEEE, pp.343~348 [58]David W. Hutchins, Fred Matteson, and Ron Roberts “TVS and Filter Combination Surface Mount Product” in 1998 IEEE, pp.999~1003 [59]K. Kelvin Hsueh, Sin-Hao, KeJeffrey Lee and Elyse Rosenbaum “UVeriESD: An ESD Verification Tool for SoC Design” in 2008 IEEE, pp.53~56 [60]Chun-Ting Lin and Shieh-Shing Lin “Application of USB high-speed signal lines in the analysis of electromagnetic interference” in Computer Technology and Materials Science, CMS 2011 [61]ANSI/ESD STM5.1-2001 [62]EN61000-4-2:2008 [63]INTEL “High Speed USB Platform Design Guidelines” [64]邱冠銘 “電子裝置靜電放電測試的模擬分析與實驗” 國立中山大學通訊工程研究所論文, 民國93年 [65]林彥輝 “高速數位電路中地彈雜訊及其電磁輻射之模擬及解決方法之研究” 國立中山大學通訊工程研究所論文, 民國94年 [66]詹奕倫 “高速數位系統中靜電放電保護元件之研究” 國立中山大學通訊工程研究所論文, 民國94年 [67]黃以上 “高速印刷電路板中靜電放電現象之理論與實驗探討” 國立中山大學電機工程學系論文, 民國92年 [68]交通大學奈米電子與晶片系統實驗室 [69]董順萍 “手持式影像裝置開關線路之靜電防護” 國立交通大學電信工程學系論文, 民國95年 [70]林俊廷 “應用於USB高速訊號線之電磁干擾分析” 2009先進電能技術研討會暨成果發表會 [71]http://www.tcl.com [72]http://www.inpaq.com.tw [73]http://amazing.ez-show.com/in/front/bin/home.phtml [74]http://www.senao.com.tw/proLife_Content.aspx?id=358 [75]http://www.us-electronics.com/files/usbconnectors.pdf
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