臺灣博碩士論文加值系統

隨著數位訊號的應用日趨成熟與普遍，高速高解析度ADC常運用於消費性產品中，如高畫質電視(High Definition TV)，第三代之行動通訊系統(3G mobile phone)，高速資料擷取系統(High speed data acquisition system)，因其訊號之頻寬大，所以都需要取樣率超過10甚至20Ms/s以上之高解析度的類比數位轉換器(Analog-to-digital converter, ADC)，管線式架構(Pipeline architecture)之類比數位轉換器能符合高取樣速度及高解析度之類比數位轉換器的設計要求。
本論文設計出每級1.5位元組成有十位元解析度每秒取樣20MHz的管線式類比數位轉換器。其架構為九階段(Stage)的管線式類比數位轉換器，前八個階段採用1.5-bit/stage的技術，最後一個階段則為一個2-bit的快閃式類比數位轉換器。取樣保持電路 (Sample-and-hold)與digital-to-Analog converter (DAC)/減法器/增益級(Multiplying DAC)使用開關電容電路來完成，最後在所有級數的輸出經由數位錯誤修正電路而得到十位元的數位輸出碼。
依據Hspice模擬結果，整個管線式類比數位轉換器可操作在20MHz之取樣頻率，在2.014MHz之輸入頻率下，其訊號雜訊失真比為54.47dB、無雜散動態範圍為59dB，有效位元數為8.76位元。

With the mature and universal of digital signal application, the high-speed and high-resolution analog to digital converter (ADC) often are used in some consumer products, such as high definition TV, the third generation of mobile communication systems, and high speed data acquisition system. Because the application on higher bandwidth requirement is growing, the need to sample more than 10 or even 20Ms/s on high-resolution ADC become more popular. The pipeline architecture used in the ADC design can meet the high sampling rate and high resolution requirement.
In this thesis, the proposed pipeline architecture has nine stages, 1.5 bits for each stage, can reach 10-bit resolution at sampling frequency of 20MHz. The first eight stages uses 1.5-bit/stage sub-ADC, compared to the last stage of a 2-bit flash analog to digital converter. Sample hold circuits, DAC, subtract, and gain stage uses the switched-capacitor (SC) circuit to realize. In the end, ten complimentary bit digital output codes are outputted by the digital error correction circuit.
Hspice simulation results show the whole pipeline analog to digital converter can operate at the sampling frequency of 20MHz; in 2.014MHz input frequency, distortion of the signal to noise ratio (SNDR) of 54.47dB, spurious-free dynamic range (SFDR) can be 59dB, and the effective number of bits 8.76 bits.

摘 要.........................................................v
Abstract......................................................vi
目 次................... ......................................vii
表目錄.........................................................ix
圖目錄.........................................................x
第一章 緒論.....................................................1
1.1 研究動機及發展現況...........................................1
1.2 論文組織....................................................2
第二章 類比數位轉換器介紹.........................................4
2.1 類比數位轉換器簡介...........................................4
2.1.1 超取樣轉換器(Oversampling A/D Converter)..................4
2.1.2 奈奎氏轉換器(Nyquist Rate A/D Converter)..................5
2.2 類比/數位轉換器的基本概念.....................................6
2.2.1 動態性能(DynamicPerformance)..............................6
2.2.2 靜態性能(Static Performance)..............................11
2.3高速類比數位轉換器架構.........................................14
2.3.1快閃式類比數位轉換器(Flash ADC)..............................14
2.3.2分時並行式類比數位轉換器(Time-Interleaved Parallel ADC).......15
2.3.3兩階段快閃式類比數位轉換器(Two-Step Flash ADC)................17
2.3.4 管線式類比數位轉換器(Pipelined ADC)..........................18
第三章 管線式類比數位轉換器架構介紹與分析.............................20
3.1 1.5位元/階段之管線式類比數位轉換器架構..........................20
3.1.1 管線式類比數位轉換器的數位錯誤更正.............................20
3.2 取樣保持電路..................................................24
3.3 倍乘式類比數位轉換器...........................................26
3.4 子類比數位轉換器...............................................27
3.5 管線式類比數位轉換器中非理想效應.................................28
3.5.1 增益誤差....................................................29
3.5.2 數位類比轉換器誤差...........................................31
3.5.3 非線性度誤差................................................32
第四章 電路設計與模擬結果...........................................35
4.1 開關式電容(Switch capacitor, SC)電路...........................35
4.1.1 MOS開關.....................................................35
4.1.2 通道電荷注入效應(Charge Injection)...........................38
4.1.3 時脈饋入效應(Clock feed-through).............................40
4.1.4 熱雜訊(thermal noise).......................................41
4.2 運算放大器(Operational Amplifier)..............................42
4.3 前端取樣保持電路(Sample and hold circuit, S/H)..................48
4.4 倍乘式數位類比轉換器(Multiplying DAC, MDAC).....................50
4.5 子類比數位轉換器(Sub-ADC).......................................54
4.5.1比較器電路....................................................54
4.5.2 1.5-bit子類比數位轉換器.......................................56
4.5.3 2-bit子類比數位轉換器.........................................57
4.6 時脈產生器(Clock Generator)....................................58
4.7 暫存器(Register)...............................................60
4.8 數位錯誤更正....................................................61
4.9 十位元管線式類比數位轉換器模擬結果.................................64
第五章 結論及未來展望................................................67
參考文獻............................................................68

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