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研究生:李元銘
研究生(外文):Yuan-Ming Li
論文名稱:設計多環和淺溝絕緣層使用65奈米技術去實現LDMOS
論文名稱(外文):Design of Multiple RESURF LDMOS with P-top rings and STI regions in 65nm CMOS Technology
指導教授:許健許健引用關係
指導教授(外文):Gene Sheu
學位類別:碩士
校院名稱:亞洲大學
系所名稱:資訊工程學系碩士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2011
畢業學年度:99
語文別:中文
論文頁數:44
中文關鍵詞:降低表面電場多層P型-頂環STI閘極場板
外文關鍵詞:STImultiple P-top ringsResurfLDMOS
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在這項工作中,一種新型的多層降低表面電場的P型-頂環的橫向擴散金氧半場效電晶體,建構在淺溝槽隔離的結構基礎上,在65奈米的基準低電壓 CMOS技術的三維 Sentaurus的製程和元件模擬。優化一個均勻電場分佈在N-漂移區可以通過的多個P型-頂環的過程,而不是過去提出的柵極場板的方法,在延長汲極漂移地區。通過這種方式,不僅都在高擊穿電壓超過40V和低導通電阻低於20米平方毫米是可以實現的,而且還影響到 WN-drift/WSTI對元件可以降低到較大的最優化的元件特性,比傳統的DIELER和分級柵場板元件更好。
In this work, a novel multiple RESURF P-top rings LDMOS with shallow trench isolation (STI) stucture based on the 65 nm baseline low-voltage CMOS technology by three-dimentsional Sentaurus process and device simulations. A optimized uniform electric filed distribution in N-drift region can be obtained by empolying the multiple P-top rings process instead of the past proposed gate field plates method in the extended drain regions. By this way, not only both of high breakdown voltage exceeded over 40V and low on-resistance below 20 m-mm2 can be achieved, but also the effect of WN-drift/WSTI ratio on device can be reduce to otain the larger optimal window of device characteristics, as compared with the conventional DIELER and graded gate field plate devices.
誌謝 7
第一章 前言 8
第二章 LDMOSFET操作原理與發展 9
2.1 LDMOSFET結構與操作原理 10
2.2 LDMOSFET的崩潰機制 10
2.3 RESURF 原理 12
2.4 RESURF LDMOSFET 13
第三章 多重場環(Multiple rings)LDMOSFET 22
3.1 Multiple P-top Rings 和STI LDMOSFET結構 22
3.2 Multiple P-top Rings 和STI LDMOSFET結構模擬與特性分析 25
3.3多重場環LDMOSFET設計方式 25
3.4多重場環LDMOSFET應用 25
3.5多重場環(Multiple rings)LDMOSFET的性能與優勢 26
第四章 多重場環與STI LDMOSFET設計與模擬 28
4.1 電性參數定義 28
4.2 LDMOSFET相關製程參數 29
4.3 3D-元件的基本架構 30
4.4建立元件及製程模擬 31
第五章 結論 41
參考文獻 42
個人簡歷 43
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[2] D. Riccardi et al., “BCD8 from 7V to 70V: a new 0.18 um Technology platform to address the evolution of applications towards smart power ICs with high logic contents”, ISPSD 2006, pp. 73-76.
[3] A. Heringa, J. Šonský, J. Perez-Gonzalez, R.Y. Su and P.Y. Chiang,
“Innovative lateral field plates by gate fingers on STI regions in deep
submicron CMOS”, ISPSD 2008, pp. 271-274.
[4] R. Pelliconi, D. Iezzi, A. Baroni, M. Pasotti, and P. L. Rolandi, “Power efficient charge pump in deep submicron standard CMOS technology”, IEEE Journal of Solid-State Circuits, Vol. 38, NO. 6, June 2003, pp. 1068-1071.
[5] Weifeng Sun, Longxing Shi, Zhilin Sun, Yangbo Yi, Haisong Li, and Shengli Lu, “High-voltage power IC technology with nVDMOS, RESURF pLDMOS, and novel level-shift circuit for PDP scan-driver IC”, IEEE Trans. Electron Devices, Vol. 53, No. 4, April 2006, pp. 891-896.
[6] P. Moens, F. Bauwens, M. Nelson, and M. Tack, “Electron trapping and
interface trap generation in drain extended pMOS transistors”, IRPS
2005, pp. 555-559.
[7] J.Šonský and A.Heringa, “Dielectric Resurf: breakdown voltage control
by STI layout in standard CMOS”, Proceedings IEDM 2005, pp.385-388.
[8] J.Šonský, G. Doornbos, A. Heringa, M. van Duuren, and J. Pérez-González, “Towards universal and voltage-scalable high gate- and drain-voltage MOSFETs in CMOS”, ISPSD 2009, pp.385-388.
[9] S. Poli, S. Reggiani, G. Baccarani, E. Gnani, A. Gnudi, M. Denison, S. Pendharkar, R. Wise, and S. Seetharaman, “Investigation on the temperature dependence of the HCI effects in the rugged STI-based LDMOS transistor” , ISPSD 2010, pp. 311-314.
[10] Yu-Hui Huang, J.R. Shih, Y.H. Lee, Sunnys Hsieh, C.C. Liu, Kenneth Wu, and H.L. Chou, “Investigation of monotonous increase in saturation-region drain current during hot carrier stress in n-type lateral diffused MOSFET with STI”, IRPS 2010, pp. 170-174.
[11] A.W. Ludikhuize, “A review of RESURF technology”, Proceedings
ISPSD 2000, pp.11-18, 2000
[12] D.R.Disney, A.K.Paul, M.Darwish, R.Basecki and V.Rumenik, “A new
800V lateral MOSFET with dual conduction paths”, Proceedings
ISPSD 2001, pp.399-402.
[13] B. J. Baliga,Power Semiconductor Devices, Copyright,by PWS ,1996.
[14] S. Colak,B. Singer,E. Stupp,“Lateral DMOS Power Transistor Design”, IEEE Electron Device Letters,Vol.EDL-1,pp.51-53,1980.
[15] 李銘富,“200V 橫向型半導體功率元件的模擬與設計”,碩士論文,國立清華大學電子工程研究所,2000.
[16]J.A Appeals,and H.M.J vaes, “High-voltage thin layer devices (RESURF
DEVICES)”Philips J.Res.35, Page:1-13,1980
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