臺灣博碩士論文加值系統

在無線通訊系統中，壓控振盪器是不可或缺的關鍵性元件。因此，如何設計具有低相位雜訊與寬頻調整範圍的壓控振盪器是一個值得探討的重點。另外，使用在射頻電路的鎊線模型也是本論文的研究重點。
本論文中的壓控振盪器是使用台積電 0.18-um CMOS製程來設計與實現。本論文研究的重點分為四大部分，第一部份介紹振盪器的應用，並討論LC振盪器的原理。第二部份提出一個低電壓、低功耗與寬頻調整範圍的LC交錯耦合振盪器，利用變容器回授，達到低相位雜訊與增加寬頻調整範圍之目標。由量測結果顯示，此壓控振盪器在中心頻率24.68 GHz偏移1 MHz 處具有 -112.53 dBc/Hz的相位雜訊，振盪頻率可從20.5 GHz調整到24.68 GHz，具有18.34 %頻率調整範圍。核心電壓0.6 V時，直流功率僅消耗2.28 mW，此晶片的面積僅有665 × 665 um2。第三部份探討向量網路分析儀所造成之誤差，並使用自製SOLT校準套件校準向量網路分析儀之誤差。第四部份是量測不同長度的鎊線，並建立其等效模型，利用π模型萃取出鎊線的參數值，並改良π模型增加鎊線模型的使用頻寬。

In communication systems, voltage-controlled oscillator (VCO) is important building blocks. Therefore, to design a VCO with low phase noise and wide-tuning range is important. In addition, this thesis also research on bonding-wire model for RF circuit applications.
In this thesis, a voltage-controlled oscillator is designed and implemented in TSMC 0.18-um CMOS process technology. Thesis research can be divided into four parts. The first part introduces the application of oscillators and discusses the theory of LC-tank VCO. A low voltage, low power and wide-tuning range voltage-controlled oscillator is presented in second part. By employing varactor feedback, the tuning mechanism is extend and improved the phase noise. Based on the proposed architecture, the measured phase noise is -112.53 dBc/Hz at 1-MHz offset from 24.68-GHz oscillation frequency, the oscillation frequency can be varied from 20.53 GHz to 24.68 GHz, and the measured tuning range is 18.34%. Operating at 0.6-V supply voltage, the VCO core consumes 2.28-mW dc power. The overall chip size including the test pad is 665 × 665 um2. The third part discusses errors of measurement in vector network analyzer, and the SOLT calibration kits are used to calibrate it. In the last part, the bonding wire model is developed base on π-model which converted from two-port network. The π-model accurately captures bonding wire characteristics beyond the self-resonant frequency.

中文摘要 i
英文摘要 ii
誌謝 iii
目錄 iv
表目錄 vii
圖目錄 viii
第一章 緒論 1
1.1 研究背景與目的 1
1.2 論文之架構 3
第二章 壓控振盪器之理論 4
2.1 振盪器原理分析 4
2.1.1 正回授振盪器 4
2.1.2 單埠負阻抗振盪器 5
2.1.3 雙埠負阻抗振盪器 8
2.2 RLC並聯共振電路 9
2.3 平面螺旋電感之損耗 11
2.3.1 導體損耗 11
2.3.2 渦旋電流損耗 12
2.3.3 基板損耗 13
2.3.4 平面螺旋電感之等效模型 13
2.4 變容器之特性 16
2.4.1 NMOS變容器 16
2.4.2 反轉型變容器 17
2.4.3 累增型變容器 18
2.5 相位雜訊 19
2.5.1 相位雜訊的定義 19
2.5.2 相位雜訊對無線通訊系統之影響 20
2.6 壓控振盪器之設計考量 21
2.7 壓控振盪器之架構 23
2.7.1 NMOS交錯耦合振盪器 23
2.7.2 互補式交錯耦合振盪器 25
2.7.3 考畢子(Colpitts)振盪器 25
第三章 低功耗寬頻壓控振盪器之設計 27
3.1 LC共振腔之設計 27
3.2 電路架構設計 30
3.3 模擬結果 34
3.4 量測結果 37
3.5 結論 42
第四章 向量網路分析儀校準 43
4.1 向量網路分析儀之硬體架構 43
4.2 向量網路分析儀的量測誤差 44
4.2.1 方向性誤差 44
4.2.2 訊號源匹配誤差 45
4.2.3 負載匹配誤差 46
4.2.4 隔離度誤差 46
4.2.5 反射路徑誤差、穿透路徑誤差 47
4.3 向量網路分析儀之誤差模型 48
4.3.1 訊號流程圖 48
4.4 SLOT校準原理 49
4.4.1 單埠校準 49
4.4.2 雙埠校準 51
4.5 自製SLOT校準套件 53
4.5.1 SOLT校準套件製作方式 54
4.5.2 搭配自製SOLT校準套件之網路分析儀設定步驟 60
4.5.3 自製SOLT校準套件量測結果 66
第五章 鎊線量測與模型之建立 69
5.1 鎊線等校模型參數萃取 69
5.1.1 考量鎊線集膚效應之等校模型 77
5.2 鎊線量測與模型之比較 78
第六章 結論 86
參考文獻 87
附錄
A 微帶線模擬 89
B 使用HFSS模擬微帶線 91
C 使用HFSS模擬鎊線 103
D 研究成果 122

[1]Delphi Corporation,“Consultation paper on the introduction of wireless systems using ultra-wideband technology,”Industry Canada, May 2005.
[2]G. Gonzalez, Microwave transistor amplifier analysis and design, Prentice-Hall, New Jersey, 1997.
[3]D.M Pozar, Microwave Engineering, 2nd edition, Wiley, New York, 1998.
[4]C. Patrick Yue and S. Simon Wong,“On-Chip Spiral Inductors with Patterned Ground Shields for Si-Based RF IC’s,”IEEE J. Solid-State Circuits, vol. 33, no.5, pp. 743–752, May 1998.
[5]Yu Cao, Robert A. Groves, Xuejue Huang, Noah D. Zamdmer, Jean-Olivier Plouchart, Richard A. Wachnik, Tsu-Jae King and Chenming Hu,“Frequency-Independent Equivalent-Circuit Model for On-Chip Spiral Inductors,”IEEE J. Solid-State Circuits, vol. 38, no.3, pp. 419–426, March 2003.
[6]卓宜賢，應用於微波及毫米波金氧半場效電晶體壓控振盪器之研製，碩士論文，國立台灣大學電信工程研究所，台北，2005。
[7]B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw, Inc. 2001
[8]B. Razavi, RF Microelectronics, PRENTICE HALL, 1998.
[9]黃琴雯，使用金氧半場效電晶體與假型高速電子移動場效電晶體之注入式鎖定除頻電路設計，碩士論文，國立臺北科技大學電腦與通訊研究所，台北，2009。
[10]T. P. Wang,“A K-band low-power Colpitts VCO with voltage-to-current positive-feedback network in 0.18-um CMOS,”IEEE Microwave and Wireless Component Letter, vol. 21, no. 4, pp. 218-220, April 2011.
[11]Aemo Yang, Choul-Young Kim, Dong-Wook Kim, and Songcheol Hong,“Design of a 24-GHz CMOS VCO With an Asymmetric-Width Transformer,”IEEE transactions on circuits and systems II, vol.57, no.3, pp.173-177, Mar. 2010.
[12]Y. H. Kuo, J. H. Tsai, T. W. Huang,“A 1.7-mW, 16.8% Frequency Tuning, 24-GHz Transformer-Based LC-VCO using 0.18-um CMOS Technology,”IEEE Radio Frequency Integrated Circuits Symp. Dig., pp. 79-82, 2009.
[13]C. A. Lin, J. L. Kuo, K. Y. Lin, and H. Wang,“A 24 GHz Low Power VCO With Transformer Feedback,”IEEE Radio Frequency Integrated Circuits Symp. Dig., pp. 75-78, 2009.
[14] C. K. Hsieh, K. Y. Kao, J. R. Tseng, K. Y. Lin,“A K-Band CMOS Low Power Modified Colpitts VCO Using Transformer Feedback,”In 2009 IEEE MTT-S International Microwave Symp. Dig., pp. 1293-1296, 2009.
[15]S. L. Liu, K. H. Chen, Tsu Chang, and Albert Chin,“A Low-Power K-Band CMOS VCO With Four-Coil Transformer Feedback,”IEEE Microwave and Wireless Component Letter, vol.20, no.8, pp. 459-461, Aug. 2010.
[16]H. H. Hsieh and L. H. Lu,“A low-phase-noise K-band CMOS VCO,”IEEE Microw. and Wireless Compon. Lett., vol. 16, no. 10, pp. 552–554, Oct. 2006.
[17]KaChun Kwok and John R. Long,“A 23-to-29 GHz Transconductor-Tuned VCO MMIC in 0.13 um CMOS,”IEEE J. Solid-State Circuits, vol. 42, no.12, pp. 2878–2886, Dec. 2007.
[18]H. H. Hsieh and L. H. Lu,“A High-Performance CMOS Voltage-Controlled Oscillator for Ultra-Low-Voltage Operations,”IEEE Trans. Microw. Theory Tech., vol. 55, no. 3, pp. 467-473, March 2007.
[19]陳建志，適用於三接收機網路分析儀之改良式TRL校正方式，碩士論文，國立成功大學電機工程學系，台南，2003。
[20]黃士釗，錫球陣列載具電路模型之建立，碩士論文，國立成功大學電機工程學系，台南，2003。
[21]R&S ZVL Vector Network Analyzer Operating Manual.
[22]JuHwan Lim, DaeHan Kwon, Jae-Sung Rieh, Soo-Won Kim, and SungWoo Hwang,“RF Characterization and Modeling of Various Wire Bond Transitions,”IEEE Trans. Adv. Packag., vol. 28, no. 4, pp. 772-778, Nov. 2005.
[23]J. C. Guo and T. Y. Tan, “A Broadband and Scalable Model for On-chip Inductors Incorporating Substrate and Conductor Loss Effects,”IEEE Radio Frequency Integrated Circuits Symp. Dig., pp. 593-596, 2005.
[24]W. Jing, L. Sun, H. Sun,“Modeling and Parameter Extraction Methods of Bond-Wires for Chip-Package Co-Design,”IEEE Electronics Packaging Technology, pp. 1-3, 2006.