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研究生:倪國宏
研究生(外文):Kwok-Wang Ngai
論文名稱:以逐步迴歸結合皮爾森相關係數近似值與逐段線性建模進行以生產週期時間為主之晶圓良率分析
論文名稱(外文):Cycle-Time-Aware Semiconductor Manufacturing Yield Analysis using Stepwise Regression with Pearson Correlation Approximation and Piecewise Linear Modeling
指導教授:范治民
學位類別:碩士
校院名稱:元智大學
系所名稱:工業工程與管理學系
學門:工程學門
學類:工業工程學類
論文種類:學術論文
論文出版年:2011
畢業學年度:99
語文別:英文
論文頁數:104
中文關鍵詞:週期時間半導體製造良率分析相關係數逐步迴歸
外文關鍵詞:Cycle TimeSemiconductor Manufacturing Yield AnalysisCorrelation CoefficientStepwise Regression
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在半導體廠中,影響良率的因子除了製程配方的設定,亦包含了週期時間。當晶圓經過特定的製程步驟之週期時間越長,越容易收到粉塵的汙染與氧化,導致晶圓鋪設的電路受損,進而影響晶圓生產的良率。除此以外,某些製程步驟中的異常事件會同時降低晶圓生產之良率與增加其生產週期時間。因此如何透過週期時間尋找影響晶圓生產良率的關鍵之製程步驟成為良率分析之重要課題。
然而以生產週期時間進行良率分析存在了四個挑戰。第一個挑戰為良率分析基於週期時間效率問題。現今半導體廠有數百道製程步驟,若逐一將所有的製程步驟間週期時間與良率進行關聯性分析,將需要大量的演算時間。第二個挑戰為週期時間與良率之離群值效應。若分析過程中離群值沒有受到考量,將不利於良率分析的結果。第三個挑戰為共變量的效應。事實上週期時間並非唯一影響良率的因子,良率分析過程中忽略了其它因子對良率的影響會誤導良率分析的結果。第四個挑戰為週期時間與良率的非線性相關效應。若良率分析過程並未考量此效應,將不利於篩選的因子對於良率變量之解釋。
針對上述四項挑戰,本論文提出了一套基於週期時間之良率分析架構。此架構包含了關鍵週期時間分析、機台良率分析以及整合式良率建模等三個模組。第一個模組,關鍵週期時間分析包含了篩選與辨視兩步驟,分別解決前兩項挑戰。在篩選的步驟中,使用了皮爾森相關係數之近似值,快速標示出與良率高度相關的製程步驟間週期時間。在辨視的步驟中,則使用了斯皮爾曼等級相關係數,穩健的找出與良率有顯著相關的製程步驟間週期時間。第二個模組,機台良率分析使用變異數分析找出影響良率關鍵的機台。第三個模組,整合式良率建模協同前兩個模組,並包含了逐段線性建模以及逐步迴歸等兩個方法以解決第三項與第四項挑戰。逐段線性建模以兩組線性模型逼近週期時間與良率之非線性相關之效應,而逐步迴歸則針對影響良率關鍵的週期時間因子與機台因子進行變數篩選,對於不同性質的因子與良率進行分析。
模擬結果指出,相較於直接使用皮爾森相關係數對週期時間進行良率分析,關鍵週期時間分析不但可以得到相似的辨視率,且擁有較佳的分析效率。除此以外,本論文提出的良率分析架構於實際晶圓半導體廠的資料驗證中,同時考量了分析效率、週期時間與良率的離群值效應、共變量效應以及非線性相關效應,找出影響良率的關鍵因子。此良率分析架構不僅可以提供工程師影響良率關鍵的因子,亦可提供這些關鍵因子額外的資訊。


In semiconductor manufacturing, yield loss is not only due to impropriate settings of individual process recipes but also associated with longer cycle time. On the one hand, wafer lot in some specific process steps with longer cycle time is more likely to be contaminated by particles or oxidized. On the other hand, an abnormal event sometime may result in low yield with longer cycle time. Therefore, cycle time has become either a direct or indirect factor to yield loss. Using cycle time data for yield analysis is a new topic in semiconductor manufacturing.
There are four challenges for cycle time analysis. The 1st challenge, C1, is high computation complexity because, with hundreds of process steps nowadays, the number of cycle time partitioned by different process steps is huge. The 2nd challenge, C2, is the outlier effect between cycle time and yield. It is inevitable and may decrease the quality of cycle time analysis. The 3rd challenge, C3, is that cycle time is not the only possible yield loss factor. Without considering other covariate effect may mislead the result of the analysis. The 4th challenge, C4, is the nonlinear correlation between cycle time and yield. Without considering the nonlinear correlation effect may reduce the variation explanation capability of a yield analysis model.
To cope with the four challenges C1~C4, a methodology framework of cycle-time-aware yield analysis is proposed in this thesis. It consists of three major modules: critical cycle time analysis (CCA), tool commonality analysis (TCA) and integrated yield modeling (IYM). The first module, CCA, sequentially conducts Screening and Identification to solve challenges C1 and C2 respectively. The Screening aims at efficiently highlighting the cycle time strongly associated with yield by using approximated Pearson correlation coefficient, whereas Identification shoots for robustly providing the cycle time significant to yield loss by applying Spearman correlation coefficient, a nonparametric correlation analysis approach. The second module, TCA, adopts an industry practice, one-against-others ANOVA (Analysis of Variance) technique, to highlight the equipment tool significant to yield loss. The third module, IYM, collaborates with CCA and TCA by applying stepwise regression with piecewise linear modeling to solve challenges C3 and C4.
Simulation study is conducted on CCA, which shows that the efficiency of approximated Pearson correlation coefficient outperforms the efficiency of standard Pearson correlation coefficient while maintaining the same accuracy of identification rate. Fab data validation demonstrates that the proposed method not only identifies several yield-loss factors but also reveals both nonlinear correlation and covariate effects of cycle time. Engineers thus benefit from obtaining additional information on the relationship among individual key factors for effective yield analysis.


CONTENTS
摘要 i
ABSTRACT iv
CONTENTS vi
Contents of Figures viii
Contents of Tables x
Chapter 1: Introduction 1
1.1 Background: Yield Enhancement in Semiconductor Manufacturing 1
1.2 Motivation & Objective: Cycle-Time-Aware Semiconductor Manufacturing Yield Analysis 3
1.3 Research Methodology 6
Chapter 2: Literature Survey 8
2.1 Semiconductor Manufacturing Data 8
2.2 Semiconductor Manufacturing Yield Diagnosis 10
2.3 Correlation and Regression Analysis Method 14
Chapter 3: Models and Problem Formulation 19
3.1 Brief Definition of Cycle Time 19
3.2. Challenge 1: Complexity of Computation 25
3.5 Challenge 2: Outlier Effect 27
3.5 Challenge 3: Covariate Effect on Cycle Time Analysis 28
3.6 Challenge 4: Non-linear Correlation Effect 32
Chapter 4: Methodology Framework 33
4.1 Introduction of Critical Cycle Time Analysis (CCA) 36
4.2 Introduction of Tool Commonality Analysis 38
4.3 Introduction of Integrated Yield Modeling Framework 40
Chapter 5: Critical Cycle Time Analysis 46
5.1 Screening 46
5.2 Identification 59
Chapter 6: Integrated Yield Modeling 62
6.1 CCA and TCA with Integrated Modeling 64
6.2 Integrated Modeling - Piecewise Linear Modeling 66
6.3 Integrated Modeling - Stepwise Regression Like Pairwise Selection 72
Chapter 7: Simulation Study and Empirical Study 78
7.1 Simulation Study for CCA 78
7.2 An Empirical Study 82
Chapter 8: Conclusions: 93
References 96
Appendix I- Simulation Study on the Distribution of t Transformed Approximated Correlation Coefficient 99
Appendix II-Transformation of Cycle Time Data 104


Contents of Figures
Figure 1 Yield level in different periods 1
Figure 2 Distribution of yield in the stage of mass production 1
Figure 3 Yield analysis with respect to different type of manufacturing data 2
Figure 4 Research Structure 7
Figure 5 Tree structure of single-step cycle time and multi-step cycle time 20
Figure 6 Number of process steps with the corresponding number of cycle time 25
Figure 7 Outlier effect between cycle time and yield 27
Figure 8 Additive effect between cycle time and yield 29
Figure 9 Confounding effect between cycle time and yield 30
Figure 10 Time constraint effect between cycle time and yield 32
Figure 11 Organization of chapter 4 35
Figure 12 Screening and Identification of CCA 37
Figure 13 Statistical tests on different equipment tool 39
Figure 14 Framework of cycle-time-aware yield analysis 40
Figure 15 Components of screening stage 46
Figure 16 Correlation tree structure 50
Figure 17 Bottom layer of the correlation tree structure 51
Figure 18 Growing of the correlation tree structure 53
Figure 19 Output of correlation tree structure by MS Excel 55
Figure 20 Correlation tree structure with color management 58
Figure 21 Components of Identification stage 59
Figure 22 Procedure of screening stage and Identification stage 61
Figure 23 Framework of cycle-time-aware yield analysis 62
Figure 24 Collaboration of CCA, TCA and IYM 65
Figure 25 Piecewise linear modeling in IYM 67
Figure 26 Scatter plot of CT and Yield 68
Figure 27 Ranked observation of CT and the cut points vs. yield 68
Figure 28 Two subsets partitioned by cut point c=21 69
Figure 29 Computation quality among different methods 81
Figure 30 Computation efficiency among different methods 81
Figure 31 Screening and Identification on the real case data 84
Figure 32 Scatter plots and correlation coefficients between cycle time and yield 84
Figure 33 Optimal cut point selection of piecewise linear modeling 86
Figure 34 Different groups partitioned by piecewise linear modeling 86
Figure 35 Scatter plot between and yield 87
Figure 36 Scatter plot between and yield 90
Figure 37 Scatter plot between and yield 90
Figure 38 c.d.f of t-transformation correlations 100
Figure 39 p.d.f of t-transformation correlations 100

Contents of Tables
Table 1 Different types of semiconductor manufacturing data 9
Table 2 Methods overview 18
Table 3 Categorizing single-step cycle time and multi-step cycle time 21
Table 4 Category of the challenge 24
Table 5 Coloring rule for color management 58
Table 6 Iterative selected cycle time yield loss factor 92
Table 7 Selected root causes with integrated yield modeling 92
Table 8 Simulation result for the t-transformation correlations 101


References
[1] Leachman, R. C. and Ding, S., “Excursion Yield Loss and Cycle Time Reduction in Semiconductor Manufacturing," IEEE Transactions on Automation Science and Engineering, 8, 112-117, January 2011
[2] Chien, C.-F, Wang, W.-C and Cheng J.-C., “Data mining for yield enhancement in semiconductor manufacturing and an empirical study," Expert Systems with Applications, 33, 192-198, 2007
[3] Chen, A. and Hong, A., “Sample-Efficient Regression Trees (SERT) for Semiconductor yield Loss Analysis," IEEE Transactions on Semiconductor Manufacturing , 23, 358-369, August 2010
[4] Krueger, D. C., Montgomery, D. C., Mastrangel, C. M., “Application of Generalized Linear Models to Predict Semiconductor Yield Using Defect Metrology Data”, IEEE Transaction on Semiconductor Manufacturing, 24, 44-58, Feburary 2011
[5] McCray, A. T., McNames, J. and Abercrombie, D., "Locating Disturbances in Semiconductor Manufacturing With Stepwise Regression," IEEE Transactions on Semiconductor Manufacturing, 18, 458-468, August 2005
[6] Wein, L. M., “On the Relationship Between yield and cycle Time in Semiconductor Wafer Fabrication," IEEE Transaction on Semiconductor Manufacturing , 5, 156-158, May 1992
[7] Srinivasan, K., Sandell, R. and Brown, S., " Correlation between Yield and Waiting Time: A Quantitative Study," IEEE/CPMT International Electronics Manufacturing Technology Symposium, 65-69, October 1995
[8] Cunningham, S. P. and Shanthikumar, J. G., " Empirical Results on the Relationship Between Die Yield and cycle Time in Semiconductor Wafer Fabrication," IEEE Transaction on Semiconductor Manufacturing, 9, 273-277, May 1996
[9] Tirkel, I., Reshef, N. and Rabinowitz , G., " In-line Inspection impact on Cycle Time and Yield," IEEE Transactions on Semiconductor Manufacturing, 22, 491-498, November 2009
[10] Tu, Y.-M and Chen, H.-N, "Capacity planning with sequential two-level time constraints in the back-end process of wafer fabrication," International Journal of Production Research, 47, 6967-6979, December 2009
[11] Chang, W.-C., Yu, M., Wu, R.-C., Chen, C., Chen, J. , C. Y., Hsieh and C. K., Wang, " Yield Improvement through Cycle Time and Process Fluctuation Analysis," IEEE International Semiconductor Manufacturing Symposium, , 267-270, October 2001
[12] L. Huang, S. Lu, R. You and K. Hsu, "Method for controlling queue time constraints in a fabrication facility," U.S. Patent, 6647397B1, 2003.
[13] Vries, D.K., Chandon., Y., “On the False-Positive Rate of Statistical Equipment Comparisons Based on the Kruskal–Wallis H Statistic”, IEEE Transaction on Semiconductor Manufacturing, 20, , august 2007
[14] R. Robert, and Y. Nishi, Handbook of semiconductor manufacturing technology, CRC Press, 2008.
[15] Cunningham, J. A., "The Use and Evaluation of Yield Models in Integrated Circuit Manufacturing," IEEE Transactions on Automation Science and Engineering, 3, 60-71, May 1990
[16] Cunningham, S. P., Spanos and C. J., Voros, K., "Semiconductor Yield Improvement: Results and Best practices," IEEE Transactions on Semiconductor Manufacturing, 8, 103-109, May 1995
[17] Bergeret, F. and Gall, C. L., "Yield Improvement Using Statistical Analysis of Process Dates," IEEE Transactions on Semiconductor Manufacturing, 16, 535-542, August 2003


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