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研究生(外文):Chia-Cheng HE
論文名稱(外文):Low Capture Power ATPG
指導教授(外文):Wang-Dauh Tseng
外文關鍵詞:ATPGmultiple scan chaintest patternlow capture power
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在晶片測試流程中,功率消耗是一個重要的議題,在本研究中,我們著重於減少在多重掃描鏈架構下的資料擷取模式(capture mode)的功率消耗(power con-sumption)。我們在自動測試資料產生器(automatic test pattern generation,ATPG)流程中,針對測試資料偵測的錯誤,可以影響多個掃描細胞(scan cell)傳導出其錯誤,但只需要選擇其中一個掃描細胞(scan cell)即可檢驗錯誤,我們讓錯誤盡量由使用率較高的掃描細胞傳導出來,以利於多重掃描鏈的分割,增加資料擷取模式下關閉的子掃描鏈數目,進而減少資料擷取模式的功率消耗。另一方面我們在測試資料產生完後合併相容的測試資料以減少測試資料集合的大小,在合併過程中以減少電路訊號異動的個數為優先考量,因此減少資料擷取模式的功率消耗。在實驗結果中,我們將這個方法套用在ISCAS’89的電路,我們產生的測試資料,在電路測試的擷取模式(capture mode)中,平均可以有效的減少約64.07%的訊號轉換活動。

With the advancement for today’s very large scale integration (VLSI) circuits, power dissipation is becoming a critical issue during design-for-test and test prepara-tion for low-power devices. In scan-based designs, the circuit states in test mode may do not exist in normal circuit operation. This results more switching activity in the cir-cuit. Power consumption during scan testing can be much greater than during normal operation. In this paper, we propose the low capture power ATPG base on the multiple scan chain architecture. In ATPG flow, the fault-effect will influence several scan cells, but we just select one of scan cells to be observed. We propagate the fault-effect to the scan cells which be observed with high utility rate, it will benefit the scan chain parti-tion, and improve the scan chain disable technique to reduce the capture power. On the other hand, during the test data compaction, we consider the switch activity in the cir-cuit and disable more sub-scan chain to merge the test data. Experimental results for the ISCAS’89 circuits have shown that this method can achieve an average reduction in capture power over 64%.

第一章、緒論 1
第二章、基礎架構 4
2.1可測試性設計 4
2.2多重掃描鏈架構 6
第三章、方法 8
3.1自動測試資料生產器概論 8
3.1.1錯誤模型 10
3.1.2自動測試資料生產器 12
3.1.3 PODEM演算法 15
3.2可測試性分析 17
3.2.1 SCOAP Testability Analysis 18
3.2.2以機率為基礎的可測試分析 19
3.3錯誤傳導的分析 21
3.4掃描鏈分割 26
3.5測試資料合併 28
第四章、實驗結果 30
第五章、結論 37
參考文獻 38

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