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研究生:張修誠
研究生(外文):Chang, HsiuCheng
論文名稱:低成本/高效率頻寬之可動態畫質調整之H.264視訊編碼器SOC架構設計
論文名稱(外文):A Low-Cost Bandwidth-Efficient H.264 Video Encoder SOC Architecture Design With Dynamic Quality-Adjustability
指導教授:郭峻因
指導教授(外文):Guo, JiunIn
口試委員:王進賢葉經緯蕭勝夫蔡宗漢莊俊雄陳晉明
口試委員(外文):Wang, JinnShyanYeh, ChingWeiHsiao, ShenFuTsai, TsungHanChuang, GeneChen, JinMing
口試日期:2012-07-23
學位類別:博士
校院名稱:國立中正大學
系所名稱:資訊工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2012
畢業學年度:100
語文別:英文
論文頁數:117
中文關鍵詞:H.264視訊編碼器動態畫質調整
外文關鍵詞:H.264 Video EncoderDynamic Quality Adjustability
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Improving memory bandwidth efficiency of multimedia system and achieving high-definition real-time video encoding are the recent design trends in power-aware portable/vehicle/surveillance video applications, but the focus was only on low-cost, low-resolution and low-power design in the past. Furthermore, it takes a lot of hardware for high-definition video encoding associated with high external memory bandwidth and complexity to speed up to meet the requirement of real-time video encoding. As a result, developing a SOC video system that takes into account both low-cost/low-power design and high-definition real-time video encoding for power-aware video applications is a daunting challenge. This dissertation presents a low-cost bandwidth-efficient SOC architecture of H.264 video encoder with dynamic quality adjustability for power-aware video applications. We implement optimization methods in algorithm, H.264 video encoder architecture and video SOC system, respectively. First, in algorithm optimization, we propose dynamic quality-adjustable algorithms for motion estimation and intra prediction that can dynamically configure the encoding modes with the design trade-off between power consumption and video quality for various video encoding applications. Because of the setting, computational complexity can be reduced by as high as 90%. We also propose two-stage fast MB-skip algorithm without recalculating SATD value of skip cost. The algorithm can be applied to static surveillance video applications, and it has 60% of bit-rate saving in the same PSNR value as compared to those without. Second, in H.264 video encoder architecture optimization, to simplify encoding flow and eliminate data dependence between memory data accessing and kernel core processing, we adopt six pipeline stages with the order of data pre-loading, integer motion estimation, fractional motion estimation, intra prediction, entropy coding/deblocking filtering and extended output frame buffering. In addition, we design a pre-load scheduler and an extended output frame buffer module for accessing source YUV, reference data and reconstructed data to achieve high efficiency data access with a MB-based scan order. According to the abovementioned optimization methods for H.264 video encoder architecture, we reduce external memory bandwidth by 70% by decreasing the number of R/W access from external memory, and enable H.264 video encoder to operate within a reasonable range in external memory bandwidth when targeting at high-definition video applications. In SOC video system optimization, we develop AXI-like system bus and dual direct memory access (DMA) architecture to decrease the latency of external memory accessing by using a bank-interleaving technique of DRAM, achieving 100% improvement for external memory bandwidth efficiency. With 70% of reduction of external memory bandwidth and 90% of computational complexity, the proposed H.264 video encoder SOC design can satisfy real-time performance requirement of HD (1280×720@30fps) and HD1080 (1920x1080@30fps) when operated at 90MHz and 160MHz at the cost of 485K gates and 15.2K bytes local memory according to TSMC 0.13um CMOS technology.
Chapter 1 Introduction
1.1 Overview of video coding systems
1.2 Design Motivation and Challenges
1.3 Organization of the Dissertation
Chapter 2 Previous Works
2.1 H.264 Video Encoding Flow
2.2 DRAM and Bus Latency in SOC System
2.3 H.264 Video Encoder Design
Chapter 3 Proposed H.264 Video Encoder: Optimization Methodology
3.1 Algorithm Optimization
3.1.1 Integer Motion Estimation (IME)
3.1.2 Fractional Motion Estimation
3.1.3 Intra Coding
3.1.4 Entropy Coding
3.1.5 In-loop Deblocking Filter (ILF)
3.1.6 Two-stage MB-skip algorithm
3.1.7 Exploiting quality modes in the proposed design
3.2 H.264 video encoder architecture optimization
3.2.1 Six-stage MB-pipelined architecture
3.2.2 Output frame buffer architecture
3.2.3 Memory replacement optimization
3.3 SOC video system optimization
3.4 Performance Evaluation
Chapter 4 Design Implementation
4.1 Design Methodology
4.2 RTL Verification Environment
4.3 FPGA Prototyping
4.4 Chip Testing
4.5 SOC Chip Prototyping
Chapter 5 Performance Comparison
Chapter 6 Conclusion
Reference
Publication List
Award List


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