臺灣博碩士論文加值系統

本論文探討於毫米波三倍頻器的設計與功率放大器以及被動混頻電路的設計。在三倍 頻器的設計，以平衡式架構，和緊縮微帶共振單元(CMRC)架構，設計出操作在 Ka-band和V-band 的毫米波三倍頻。在功率放大器方面，使用分佈式架構增加頻寬與串接(cascode)方式提出改良，使得電路可以增加頻寬和增益;在混頻器方面使用電阻式混頻機制，達到直流零損耗等優點。
在第二章研製了一 個應用於Wimax頻帶的 功率 放大 器。這個利用0.15-μm pHEMT 實現的三級分佈式功率放大器，呈現了訊號最大增益於12dB，以及在2~3GHz時輸出功率有31dBm。第三章介紹了一個Ka-band三倍頻器使用共平面波導（CPW）與集總元件構成巴倫電路。巴倫的測量結果表明，1 dB增益平衡，從11.6 GHz的10度到13 GHz的相位平衡。一個諧振電感電容（LC）濾波器用來消除一倍頻;相位延遲線，以加強輸出的三次諧波。在36GHz，最低轉換損耗為6.7dB，在13 dBm的輸入功率達到了三倍頻;壓抑一倍頻和二次諧波差值分別為24dB和27dB。
於第四章三倍頻MMIC晶片的設計面積為1mm2的晶片尺寸。三倍頻器結合緊湊微帶諧振單元（CMRC）結構，抑制諧波與電流重用技術，以提高轉換增益。在60 GHz，16.6 dB的轉換增益為8 dBm的輸入功率達到了三倍頻;壓抑一倍頻和二次諧波頻率分別為22分貝和27分貝。電阻混頻器具有低轉換損耗低LO功率水平。這使得電路具有良好的LO-RF隔離度，並增進了RF和IF匹配網絡的設計。使用0.15-μm pHEMT技術製造，晶片面積為1.7×0.7 mm2。它達到57至60 GHz的RF頻率在12至16 dB損耗，輸入三階截取點（IIP3）為7 dBm。

The dissertation includes MMIC chips such as distributed power amplifiers, Ka-band triplers, two V-band CMRC triplers and V-band balance resistive mixers.
The design and implementation of the MMIC chips for WiMAX power amplifier applications as well as RF passive circuits are performed. Three stages of cascode gain cell are used in this design to enhance the gain and bandwidth performance. To improve the stability of the circuit, a damping resistor is added to the gate of the common gate amplifier in the cascode pair. Power consumption and current of the distributed amplifier are 2980mW and 298mA at 10V supply voltage, respectively. The chip area is 2.3 mm2 including all test pads.
The design of integrated compact tripler MMIC is performed to achieve high performance for the Ka-band frequency applications. This design describes a lumped-element balun for use in a miniature, coplanar waveguide (CPW) frequency tripler pseudomorphic high electron mobility transistor (pHEMT) microwave monolithic integrated circuit (MMIC). The measurement results of the balun show a 1-dB gain balance and a 10 degrees phase balance from 11.6 GHz to 13 GHz. It was used in the design of a 36-GHz monolithic tripler at the input port. A resonant inductor-capacitor (LC) filter was used to eliminate the fundamental frequency and a phase delay line was employed to enhance the third harmonic in the tripler. At 36 GHz, the tripler achieved a minimum conversion loss of 6.7 dB at an input power of 13 dBm; the suppressions of the fundamental and second harmonic frequencies were 24 dBc and 27 dBc, respectively.
The design of the second integrated tripler MMIC chip is also performed with miniature chip size of only 1 mm2. This tripler combines the compact microstrip resonant cell (CMRC) topology for suppress unwanted harmonic and current-reuse technique to improve the conversion gain. At 60 GHz, the tripler achieved a minimum conversion gain of -16.6 dB at an input power of 8 dBm; the suppressions of the fundamental and second harmonic frequencies were 22 dBc and 27 dBc.
The proposed resistive mixer has low conversion loss at a low LO power level. This enables the circuit to have well LO-RF isolation and facilitates an RF and IF matching network design. The fabricated chip size using 0.15-μm pHEMT technology is 1.7 × 0.7 mm2. It achieves a conversion loss of 12 to 16 dB at an RF frequency of 57 to 60 GHz, and the input-referred third-order intercept point (IIP3), which is 7 dBm.

Table of Contents
Abstract....................................................................................................viii
Figure Captions........................................................................................xiii
Table Captions.........................................................................................xviii
Chapter 1 Introduction.............................................................................1
1-1 Background...................................................................................1
1-2 Wireless Communication system..................................................3
1-2-1 WiMAX system .................................................................4
1-2-2 Millimeter wave Systems ..................................................6
1-3 Thesis Organization.......................................................................8
Chapter 2 Distributed Power Amplifier Design………….…………..11
2-1 Introduction ..................................................................................11
2-2 Circuit Analysis…........................................................................14
2-3 Circuit Design………………………….…………………..........18
2-4 Experimental results…………………….……………………….20
2-5 Summary.......................................................................................24
Chapter 3 A High Efficient Ka Band MMIC Frequency Tripler Using Lumped-Element Balun……………………………………..26
3-1 Introduction ..................................................................................26
3-2 Circuit Design ..............................................................................27
3-2-1 Mathematical Formulation................................................29
3-2-2 Coplanar Waveguide Delay Line ......................................33
3-2-3 Evaluation of an Improved Lumped Element Marchand
Balun.................................................................................34
3-3 Proposed Tripler within Marchand Baluns...................................37
3-4 Experimental results…………………….……………………….38
3-5 Summary ......................................................................................44
Chapter 4 A V-band Tripler Using CMRC Structure............................45
4-1 Introduction ..................................................................................45
4-2 CMRC Theory...............................................................................47
4-3 V-Band Bandpass Filter Design....................................................51
4-4 Circuit Design................................................................................52
4-5 Experimental Results ....................................................................54
4-6 Summary……................................................................................59
Chapter 5 Low Conversion-Loss tripler Incorporating CMRC for
V-band Applications………………….....................................61
5-1 Introduction .....................................................................................61
5-2 Asymmetric CMRC Design.............................................................62
5-3 Circuit Design..................................................................................66
5-4 Experimental results.........................................................................67
5-5 Summary...........................................................................................74
Chapter 6 A V-band Balance Resistive Mixer..........................................75
6-1 Introduction ......................................................................................75
6-2 Circuit Design...................................................................................76
6-2-1 Machand Balun....................................................................78
6-2-2 Lumped Element Balun ......................................................81
6-2-3 Architectures of mixers........................................................84
6-3 Experimental results..........................................................................87
6-4 Summary...........................................................................................92
Chapter 7 Conclusion and Future Works.................................................94
7-1 Conclusions………………………………………………………...94
7-2 Suggestions for future works……………………………………....96
References ..................................................................................................96
Publication List .........................................................................................108
Figure Captions
Figure 1-1 Frequency band designation (*IEEE Std. 521-2002, IEEE Standard Letter Designations for Radio-Frequency Bands)
Figure 1-2 Various applications of the modern wireless transceiver systems.
Figure 1-3 The basic structure of RF front end transceiver module
Figure 1-4 Speed versus mobility of wireless systems: Wi-Fi, High Speed Packet Access (HSPA), Universal Mobile Telecommunications System (UMTS), GSM
Figure 1-5 shows the available spectrum for indoor wireless communication around the world
Figure 1-6 Organization chart of the thesis.
Figure 2-1 A common architecture of a DPA
Figure 2-2 (a) Common-source gain stage. (b) Cascode gain stage with series- peaking inductor (Lx).
Figure 2-3 Schematic of distributed power amplifier.
Figure 2-4 Microphotograph of the distributed power amplifier.
Figure 2-6 Simulated and measured input and output return loss versus frequency
Figure 2-7 Measured output power (dBm), PAE (%) and gain (dB) at 2.4 GHz of the distributed power amplifier. (Vd=10 V, Vg1=5 V, Vg2=-0.85 V)
Figure 2-8 Measured output power versus frequency
Figure 2-9 Measured output third order intercept versus frequency.
Figure 3-1 Full circuit schematic of the 36-GHz pHEMT balanced frequency tripler.
Figure 3-2 Frequency versus output current spectrum of
(a) output current I1
(b) output current I2
(c) total output current IT
Figure 3-3 Simulated results of the phase shifter with coplanar waveguide structure at resonant frequency of 36 GHz.
Figure 3-4 Microphotograph of the Lumped-element balun
(a) Chip photograph of the balun (0.6 mm x 0.4 mm).
(b) The lumped -element balun equivalent circuit. L and C are lumped elements.
Figure 3-5 Simulated and measured results of S21 and S31 of the proposed Marchand Balun(a) Insertion losses (b) Phase difference.
Figure 3-6 Microphotograph of the fabricated tripler.
Figure 3-7 Measured and simulated output power as a function of input power at 12 GHz.
Figure 3-8 Measured and simulated output power as function of frequency at input power of 13 dBm.
Figure 3-9 Measured and simulated conversion loss as a function of input power at 36 GHz.
Figure 3-10 Measured and simulated suppression as a function of input power at 36 GHz.
Figure 3-11 Output spectrum of the proposed tripler.
Figure 3-12 Measured phase-noise spectra comparison between the tripler output and Agilent E8257D Signal Generator output
(a) Measured the tripler phase noise at 36 GHz
(b) Measured the Signal Generator phase noise at 12 GHz
(c) Measured the Signal Generator phase noise at 36 GHz
Figure 4-1 One-dimensional CMRC.
Figure 4-2 (a) CMRC structure. (b) The lumped -element CMRC equivalent circuit. (C) Simulated s-parameters.
Figure 4-3 Full circuit schematic of the 60-GHz pHEMT current reuse frequency tripler
Figure 4-4 Microphotograph of the fabricated tripler.
Figure 4-5 Measured output power as a function of input power at 20 GHz.
Figure 4-6 Measured and simulated output power as function of frequency at input power of 8 dBm.
Figure 4-7 Measured conversion gain as a function of input power at 60GHz
Figure 4-8 Measured suppression as a function of input power at 60GHz
Figure 4-9 Measured phase-noise spectra comparison between the tripler output and Agilent E8257D SignalGenerator output
(a) Measured the tripler phase noise at 60 GHz
(b) Measured the Signal Generator phase noise at 20 GHz
(c) Measured the Signal Generator phase noise at 60 GHz
Figure 5-3 Some structures of open-circuited stub type bandstop filters.
Figure 5-4 ACMRC and the equivalent circuit model.
Figure 5-5 Structure of CMRC-A.
Figure 5-6 CMRC-A simulation results of S-parameter.
Figure 5-7 Structure of CMRC-B.
Figure 5-8 CMRC-B simulation results of S-parameter.
Figure 5-9 Full circuit schematic of the 60-GHz pHEMT CMRC frequency tripler
Figure 5-10 Chip photograph of the tripler with a chip size of 1mm2.
Figure 5-11 Measured and simulated output power as a function of input power at 20 GHz.
Figure 5-12 Measured output power as function of frequency at input power
of 0 dBm.
Figure 5-13 Measured conversion gain as a function of input power at 60 GHz.
Figure 5-14 Measured suppression as a function of input power at 60 GHz.
Figure 5-15 Measured phase-noise spectra comparison between the tripler output and Agilent E8257D Signal Generator output
(a) Measured the tripler phase noise at 60 GHz
(b) Measured the Signal Generator phase noise at 20 GHz
(c) Measured the Signal Generator phase noise at 60 GHz
Figure 6-1 Schematics of balance resistive mixer.
Figure 6-2 Conventional Marchand balun
Figure 6-3 The planar Marchand microstrip balun.
Figure 6-4 Simulated the return loss and insertion loss of marchand balun
Figure 6-5 Simulated the phase and amplitude performance of marchand balun
Figure 6-6 Second-order lumped element balun schematic
Figure 6-7 Simulated the return loss and insertion loss of lumped element balun
Figure 6-8 Simulated the phase performance of lumped element balun
Figure 6-9 Single mixer circuit. (a) Passive circuit. (b) Active circuit.
Figure 6-10 Block diagram of the single-balanced mixer. (a) RF balanced mixer. (b) LO balanced mixer.
Figure 6-11 Block diagram of doubly-balanced mixer.
Figure 6-12 Chip photo of balance resistive mixer.
Figure 6-13 Measurement conversion loss of RF frequency at LO power 0 dBm, IF power 0 dBm, and fixed IF frequency at 2.4 GHz.
Figure 6-14 Measured Conversion loss of the mixer versus the LO power.
Figure 6-15 Measured conversion loss versus gate bias.
Figure 6-16 Measured conversion loss versus IF frequency of the balance resistive mixer.
Figure 6-17 Measured LO-to-IF, and LO-to-RF versus LO frequency.
Figure 6-18 Measured RF-to-IF isolations versus RF frequency.
Figure 6-19 Measured of P1dB and IIP3 at fixed LO/IF frequencies of 57.6 and 2.4 GHz.
Table Captions
Table 2-1
WiMAX system specification.
Table 2-2
Benchmark of Previous GaAs pHEMT broadband power amplifiers.
Table 3-1
The phase noise comparison table of various tripler and signal generator.
Table 4-1
The phase noise comparison table of various tripler and signal generator.
Table 5-1
The phase noise comparison table of various tripler and signal generator.
Table 5-2
Comparison of reported millmeter-wave triplers.
Table 6-1
Benchmark of Previous V-band balance resistive mixer.

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