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研究生:李偉平
研究生(外文):Wei Ping Lee
論文名稱:藉由快速熱退火及氟離子佈植改善DRAM元件可靠度
論文名稱(外文):DRAM Device Reliability Improvement by Rapid Thermal Anneal and Fluorine Passivation
指導教授:王哲麒賴朝松
指導教授(外文):J.C. WangC.S. Lai
學位類別:碩士
校院名稱:長庚大學
系所名稱:電子工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2012
畢業學年度:100
論文頁數:91
中文關鍵詞:資料儲存動態隨機存取記憶體可靠度高溫熱退火離子佈植
外文關鍵詞:retentionDRAMreliabilityhigh temperature annealF implant
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動態隨機存取記憶體為計算器領域不可或缺的重要元素,目前產品趨勢的發展,除了一般標準型DRAM外,對於行動型DRAM與伺服器型DRAM的需求也日益增加,如何維持相同的資料儲存時間更是一大挑戰。本研究中,對40奈米DRAM產品分別進行超高溫閘極介電層熱退火以及氟離子佈植之研究,藉由修補介電層界面的缺陷與增加介電層鍵結強度,在可靠度相關之TDDB、HCS以及NBTI測試中,皆可發現陣列元件和周邊電路的元件可靠度被改善,並發現此兩種方法可以減少陣列元件的漏電流,對於DRAM產品的資料儲存特性也有明顯的提升,超高溫閘極介電層熱退火對於retention損壞數,在長時間熱退火的條件下,有24.2%的改善,而RTS損壞數也分別有44.9%的改善,另外在氟離子佈植之研究中,最佳的實驗條件對於retention損壞數有34.6%的改善,而RTS損壞數也有20.5%的改善。
Dynamic random access memory is an important element in computer field. In current trending of market demand, not only standard DRAM, but also mobile DRAM and server DRAM become high growing products. It is a big challenge to have same or better quality, especially in data retention time.
In this study, high temperature rapid thermal annealing on gate dielectric layer and fluorine ion implantation in 40nm DRAM product are investigated, respectively. Defects and interface states close dielectric/Si interface are passivated and the bonding strength of dielectric layer is increased. The results of TDDB, HCS and NBTI in reliability testing are improved in the array devices and periphery device. Both two methods can be used to reduce the leakage phenomenon of the array device and better data retention characteristics.
In high temperature rapid thermal annealing on gate dielectric layer, the retention fail counts are improved about 24.2% for long time anneal, and RTS fail counts are improved about 44.9%. The best of fluorine ion implantation condition has 34.6% improvement, and RTS are improved 24.3%.
目錄
誌謝……………………………………………………………………...iv
摘要……………………………………………………………………….v
Abstract…………………………………………………………………..vi
目錄……………………………………………………………………..vii
表目錄…………………………………………………………………...ix
圖目錄…………………………………………………………………….x
第一章 簡介……………………………………………………………...1
1-1 背景 …………………………………………………………………1
1-2 基本DRAM結構與S-Fin元件……………………………………...1
1-3資料儲存時間及隨機電信信號特性………………………………...2
1-4元件可靠度介紹……………………………………………………...3
1-4-1 時間相依介電層崩潰時間(TDDB) ……………………..4
1-4-2 熱載子效應(HCS) ……………………………………….5
1-4-3 負偏壓溫度不穩定性(NBTI) …………………………...6
1-5 研究動機與方法…………………………………………………….6
第二章 藉由超高溫閘極介電層熱退火處理提升元件可靠度及資料儲
存特性………………………………………………………….12
2-1 簡介……………………………………………………………12
2-2 實驗……………………………………………………………13
2-3結果與討論……………………………………………………..14
2-3-1 S-Fin元件基本電性(ID-VG,Gm,ICP)分析………………14
2-3-2 元件可靠度(TDDB,HCS,NBTI)分析………………...16
2-3-3 DRAM資料儲存特性(retention time,RTS)分析……….18
2-4 總結…. ………………………………………………………..20
第三章 藉由氟離子佈植提升元件可靠度及資料儲存特性………….43
3-1 簡介……………………………………………………………43
3-2 實驗……………………………………………………………43
3-3 結果與討論……………………………………………………45
3-3-1 周邊電路元件基本電性分析…………………………..45
3-3-2 S-Fin元件基本電性(ID-VG,ICP)分析…………………...46
3-3-3 元件可靠度(TDDB,HCS,NBTI)分析………………...46
3-3-4 DRAM資料儲存特性(retention time,RTS)分析……….48
3-4 總結……………………………………………………………49
第四章 結論與未來研究方向………………………………………….67
4-1 結論…………………………………………………………….67
4-2 未來研究方向………………………………………………….68
參考文獻………………………………………………………………...69

表目錄
表1-1 TDDB測試的四種模式………………………………………......8

圖目錄
圖1-1 基本的DRAM架構圖…………………………………………..9
圖1-2 一個單細胞陣列結構…………………………………………...9
圖1-3 (a) Random Telegraph Signal-RTS產生的原因(b)不同溫度下所
量測的RTS特性………………………………………………10
圖1-4 熱載子效應機制圖…………………………………………….11
圖1-5 陣列元件結構圖及可能的漏電路徑…………………………...12
圖2-1 超高溫熱退火實驗製程流程圖………………………………...21
圖2-2 S-Fin結構(a)Bit-line方向(b) Word-line方向的閘極結構TEM
圖……………………………………………………………….22
圖2-3 S-Fin元件在三種HTA條件下的電流對電壓特性曲線
(VG=-1~1.5V)…………………………………………………..23
圖2-4 GIDL電流穿遂機制的能帶圖………………………………...23
圖2-5 S-Fin元件在三種HTA條件下電壓對電流特性曲線
(VG=-0.2~1V)…………………………………………………..24
圖2-6 S-Fin元件在三種HTA條件下Gm-VG曲線…………………...24
圖2-7 Charge Pumping量測方式…………………………………….25
圖2-8 S-Fin元件在三種HTA條件下所量測的Charge Pumping電
流……………………………………………………………….25
圖2-9 S-Fin元件在bit-line方向(a) w/o Anneal (b) HTA_LT的TEM
結構圖………………………………………………………….26
圖2-10 S-Fin元件在word-line方向(a)w/o Anneal (b)HTA_LT的TEM
結構圖………………………………………………………….27
圖2-11 圖(a)為周邊電路PMOS (b)w/o Anneal (c)HTA_LT的TEM結
構圖…………………………………………………………….28
圖2-12 圖(a)為周邊電路PAOX (b)w/o Anneal (c)HTA_LT的TEM結構
圖……………………………………………………………….29
圖2-13 S-Fin元件在三種HTA條件下在100℃的環境利用CVS
(a)5.3V (b) 5.45V (c) 5.6V所量測的TDDB韋伯分佈圖…….30
圖2-14 S-Fin元件在三種HTA條件下在125℃的環境利用CVS
(a)5.3V (b) 5.45V (c) 5.6V所量測的TDDB韋伯分佈圖…….31
圖2-15 S-Fin元件在三種HTA(a) w/o Anneal (b) HTA_SL (c) HTA_LT
條件下在100℃的環境下利用CVS所量測的TDDB韋伯分佈
圖……………………………………………………………….32
圖2-16 S-Fin元件在三種HTA(a) w/o Anneal (b) HTA_SL (c) HTA_LT
條件下在125℃的環境下利用CVS所量測的TDDB韋伯分佈圖……………………………………………………………….33
圖2-17 S-Fin元件在三種HTA的條件在100℃的環境下,所預測的生
命週期………………………………………………………….34
圖2-18 S-Fin元件在三種HTA的條件在125℃的環境下,所預測的生
命週期………………………………………………………….34
圖2-19 PMOSFET元件在三種HTA條件下在100℃的環境利用CVS
(a) 3.5V (b) 3.6V (c) 3.7V所量測的TDDB韋伯分佈圖……..35
圖2-20 PMOSFET元件在三種HTA(a) w/o Anneal (b) HTA_SL (c)
HTA_LT條件下在100℃的環境下利用CVS所量測的TDDB
韋伯分佈圖…………………………………………………….36
圖2-21 PMOSFET元件在三種HTA的條件在100℃的環境下,所預
測的生命週期……………………………….…………………37
圖2-22 S-Fin元件熱載子效應測試示意圖…………………………...37
圖2-23 S-Fin元件在三種HTA的條件下熱載子效應測試結果……...38
圖2-24 HTA_LT PMOSFET元件NBTI測試在不同時間下的ID-VG特
性曲線………………………………………………………….38
圖2-25 PMOSFET元件在三種HTA的條件下NBTI測試結果………39
圖2-26 DRAM資料儲存特性測試電路圖……………………………39
圖2-27 三種HTA條件下,不同的負的字元線電壓測試元件損壞
數……………………………………………………………….40
圖2-28 三種HTA條件下,不同的基底電壓測試元件損壞數………..40
圖2-29 三種HTA條件下,不同的重新寫入時間測試元件損壞率…..41
圖2-30 三種HTA條件retention測試的損壞數……………………….41
圖2-31 三種HTA條件RTS測試的損壞數……………………………42
圖3-1 氟離子佈植進入閘極介電層機制圖………………………….50
圖3-2 氟離子佈植實驗製程流程圖………………………………….51
圖3-3 氟離子佈植能量(a)10keV (b)15keV (c)20keV模擬氟離子分佈
圖……………………………………………………………….52
圖3-4 四種F-IMP條件下(a)NAOX (b)PAOX元件,電性厚度量測分
佈圖…………………………………………………………….53
圖3-5 四種F-IMP條件下(a)NAOX (b)PAOX元件,臨限電壓量測分
佈圖…………………………………………………………….54
圖3-6 四種F-IMP條件下(a)NAOX (b)PAOX元件,啟動電流量測分
佈圖…………………………………………………………….55
圖3-7 四種F-IMP條件下(a)NAOX (b)PAOX元件,轉導最大值量測
分佈圖…………………….……………………………………56
圖3-8 S-Fin元件在四種F-IMP條件下的電流對電壓特性曲線
(VG=-0.5~2V)…………………………………………………..57
圖3-9 S-Fin元件在四種F-IMP條件下所量測的Charge Pumping電
流……………………………………………………………….57
圖3-10 S-Fin元件在四種F-IMP條件下在100℃的環境利用CVS
(a)5.45V (b) 5.6V (c) 5.75V所量測的TDDB韋伯分佈圖…...58
圖3-11 S-Fin元件在四種F-IMP (a) w/o F-IMP (b) F-dose_L (c)
F-dose_M (d) F-dose_H條件下在100℃的環境下利用CVS所
量測的TDDB韋伯分佈圖……………………………………..59
圖3-12 S-Fin元件在四種F-IMP的條件在100℃的環境下,所預測的
生命週期……………………………………………………….60
圖3-13 PMOSFET元件在四種F-IMP條件下在100℃的環境利用CVS
(a) 3.5V (b) 3.6V (c) 3.7V所量測的TDDB韋伯分佈圖……..61
圖3-14 S-Fin元件在四種F-IMP (a) w/o F-IMP (b) F-dose_L (c)
F-dose_M (d) F-dose_H條件下在100℃的環境下利用CVS所
量測的TDDB韋伯分佈圖…………………………………….62
圖3-15 PMOSFET元件在四種F-IMP的條件在100℃的環境下,所預
測的生命週期………………………………………………….63
圖3-16 S-Fin元件在四種F-IMP的條件下熱載子效應測試結果……63
圖3-17 PMOSFET元件在四種F-IMP的條件下VG= -3.0V NBTI測試
結果…………………………………………………………….64
圖3-18 四種F-IMP條件下,不同的負的字元線電壓測試元件損壞
數……………………………………………………………….64
圖3-19 四種F-IMP條件下,不同的基底電壓測試元件損壞數……...65
圖3-20 四種F-IMP條件retention測試的損壞數……………………..65
圖3-21 四種F-IMP條件RTS測試的損壞數………………………….66
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