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研究生:涂永錫
研究生(外文):YUNG HSI TU
論文名稱:低折射率光子晶體邏輯元件之研究
論文名稱(外文):Low refractive index Photonic crystal study of the logic elements
指導教授:林晏瑞林晏瑞引用關係
指導教授(外文):Yen-Juei, Lin
口試委員:莊為群李偉裕
口試委員(外文):Wen-Chung ChangWei-Yu Lee
口試日期:2012-07-20
學位類別:碩士
校院名稱:中華科技大學
系所名稱:機電光工程研究所碩士班
學門:工程學門
學類:機械工程學類
論文種類:學術論文
論文出版年:2012
畢業學年度:100
語文別:中文
論文頁數:52
中文關鍵詞:邏輯閘光子晶體平面波展開法時域有限差分法光電半導體高分子材料
外文關鍵詞:Logic gatesPhotonic crystalPlane Wave Expansion MethodFinite -Difference-Time-DomainOpto SemiconductorsPolymer materials
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在近20年,光子晶體週期性的介電質材料,其有趣與奇特的電磁特性研究,在各個領域的應用一直引人注目。本論文以平面波展開法(Plane Wave Expansion, PWE) 與有限差分時域(Finite-Difference Time-Domain, FDTD)模擬分析光子晶體結構,並藉其特性設計出光子晶體邏輯閘元件,證實在入射波長為1.55μm亦有極高的傳輸效率。

研究中,我們採用OG高分子材料為介電質柱,在二維平面上製作光子晶體結構,調整中間干涉及耦合區域,使光有效侷限於結構中,達到光邏輯閘的功能,具微小化及方便化,且有效將光信號處理元件整合,成為光通訊技術上的重要元件。

In the past 20 years, photonic crystal periodic dielectric materials, with interesting and unusual magnetic properties, applications in various fields has been remarkable. This paper is the Plane Wave Expansion method (PWE) and Finite-Difference Time Domain (FDTD) simulation of photonic crystal structures, and by its characteristic design a Optical logic gates components ,confirmed the incident wave length 1.55μ m also very high transmission efficiency.
In the study, we used OG Macromolecule dielectric material for the column in the two-dimensional plane photonic crystal structure. To adjust the middle of interference and the coupling region so that light effectively confined to the structure, with achieve sub-wave – de-multiplexing functions. It has the advantage of miniaturization and convenience, and effective integration of the Optical logic gates, as important components of optical communication technology.

目錄

中文摘要 i

英文摘要 ii

目錄 v

圖目錄 vii


一、 緒論 1

1.1 光子晶體簡介 1

1.2 研究目的與方法 5

1.3 論文架構 7

二、 光子晶體基本概念 8

2.1 光子晶體的種類 8

2.2 光子晶體的應用 10

三、數值模擬分析及計算 16

3.1 平面波展開法 16

3.2 有限時域差分法 22

3.2.1 FDTD 形式 22

3.2.2 二維FDTD 形式 26

3.3 頻帶結構分析 30

3.3.1 一維系統 30

3.3.2 二維系統 32

四、 光子晶體之分析與應用 36

4.1 光子晶體波導 37

4.2 光子晶體結構的晶格型態分析 39

4.3 週期光子晶體設計光邏輯閘元件 42
4.3.1或閘 ( OR Gate ) 42
4.3.2 及閘 ( AND Gate ) 44
4.3.3 互斥或閘 ( XOR Gate ) 46

五、 結論及未來發展 48

參考文獻 49

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