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研究生:林正中
研究生(外文):CHING-CHUNG LIN
論文名稱:有效的二維離散小波轉換VLSI架構
論文名稱(外文):An Efficient VLSI Architecture of 2DDiscrete Wavelet Transform
指導教授:陳俊勝
指導教授(外文):Chun-Shen Chen
口試委員:蘇純賢劉竹峯陳俊勝
口試委員(外文):Chun-Hsien SuJu-Feng LiuChen-Chun shen
口試日期:2012-07-14
學位類別:碩士
校院名稱:中華科技大學
系所名稱:電子工程研究所在職專班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2012
畢業學年度:100
語文別:中文
論文頁數:50
中文關鍵詞:離散小波轉換
外文關鍵詞:discrete wavelet transform
相關次數:
  • 被引用被引用:0
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  • 下載下載:10
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離散小波轉換(Discrete Wavelet Transform)在訊號分析與影視訊資料壓縮
等方面受到高度的重視,訊號經過小波轉換之後可被分為低頻與高頻頻帶,根據
不同頻帶的差異性,便可以對其特性做不同的處理而達到訊號處理的目的。為了
將離散小波轉換應用於影音等多媒體資料之即時處理,就必須考量以硬體實現的
速度需求優勢。傳統離散小波轉換硬體架構設計以迴旋計算 (convolution-based)
方法為基礎,此方法所耗費的計算量相當大。因此在1996年由Sweldens提出上提
式離散小波轉換(lifting-based Discrete Wavelet Transform),此新一代的離散小
波轉換有計算效率提高、節省記憶體空間之優點,故其硬體架構為研究的重點。
近年來,有許多一維(one-dimension)及二維(two-dimension)之上提式離散小
波轉換的硬體架構被提出。惟對於二維運算仍需有外部記憶體暫存一維運算出之
中間值。本論文提出一個高效率的二維上提式離散小波轉換電路架構,使用管線
式與摺疊的技巧分別提高時脈速度與降低運算單元,同時重複使用內部暫存器以
免除外部記憶體使用之需求來提升運算效能,本電路架構經過Verilog-HDL編碼
後,以Modelsim來模擬,並搭配Matlab顯示圖形驗證,最後燒錄於 FPGA 而完
成一具有立即處理功能的離散小波轉換VLSI電路架構。
關鍵字:離散小波轉換、上提式
The discrete wavelet transform (DWT) attaches great importance on signal
analysis and data compression. The signal is divided into low-frequency and
high-frequency subbands after the wavelet transform. It achieves signal processing
goals in accordance with the different properties of each subband. When DWT is
applied to real-time multimedia processing, the speed benefit of hardware
implementation must be considered. Traditionally, DWT architecture was
convolution-based and needs extra large computations. In 1996, lifting-based DWT
was proposed by Sweldens. This scheme has the advantages of high-computation and
memory savings. This makes it an important research issue. In recent years, there are
many one-dimensional and two-dimensional DWT hardware architecture based on
this proposed scheme. It also needs external memory to store temporary results for
two-dimension processing. In this thesis, an efficient architecture for the
implementation of two-dimension, lifting-based DWT has been proposed .The folded
and the pipelined schemes were also applied. They support greater hardware
utilization and sped up clock rates. The reuse of internal registers is applied for the
removal of external memory. The proposed architecture was coded using
Verilog-HDL initially, simulated by Modelsim, and verified by Matlab. Finally, it was
implemented in an FPGA for an outcome in DWT VLSI architecture for real-time
processing applications.
Keywords: discrete wavelet transform, lifting
目錄
Abstract--------------------------------------------------------------------------------------------- i
摘要------------------------------------------------------------------------------------------------ ii
關鍵字:離散小波轉換、上提式----------------------------------------------------------- ii
目錄----------------------------------------------------------------------------------------------- iii
圖目錄----------------------------------------------------------------------------------------------v
表目錄--------------------------------------------------------------------------------------------vii
第一章 緒論--------------------------------------------------------------------------------------1
第一節 研究動機--------------------------------------------------------------------------1
第二節 研究背景--------------------------------------------------------------------------1
第三節 論文架構--------------------------------------------------------------------------2
第二章 離散小波轉換--------------------------------------------------------------------------3
第一節 前言--------------------------------------------------------------------------------3
第二節 離散小波轉換與影像壓縮-----------------------------------------------------4
第三節 上提式離散小波轉換-----------------------------------------------------------5
壹、上提式離散小波轉換基本架構---------------------------------------------6
貳、5/3 小波係數架構--------------------------------------------------------------8
第四節 二維一階離散小波轉換------------------------------------------------------ 11
第三章 數位電路設計軟體與FPGA概述------------------------------------------------ 13
第一節 Verilog硬體描述語言介紹-------------------------------------------------- 13
第二節 數位電路設計------------------------------------------------------------------ 15
第三節 FPGA編程元件---------------------------------------------------------------- 19
第四章 管線摺疊架構------------------------------------------------------------------------ 24
第一節 前言------------------------------------------------------------------------------ 24
第二節 上提式離散小波轉換的管線摺疊式架構--------------------------------- 24
第三節 5/3 濾波器架構之硬體實現------------------------------------------------- 25
第四節 二維基本架構---------------------------------------------------------------- 26
第五章 電路架構設計------------------------------------------------------------------------ 29
第一節 前言------------------------------------------------------------------------------ 29
第二節 二維離散小波轉換架構------------------------------------------------------ 29
第三節 模擬結果------------------------------------------------------------------------ 32
第六章 結論------------------------------------------------------------------------------------ 37
參考文獻----------------------------------------------------------------------------------------- 38
作者簡介----------------------------------------------------------------------------------------- 41
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