# 臺灣博碩士論文加值系統

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 In this thesis, we design CMOS quadratic polynomial circuit using best fit method and four-segment method. The propose of this thesis is based on CMOS current-mode quadratic function circuits, its W/L ratio and construction could be adjusted by the relative error that the users needed. First we explain how to implement CMOS current-mode quadratic circuits and design the proposed circuit in the way of multiple corrections. We use the best fit CMOS quadratic polynomial circuit to realization exponential function. The imitative result based on the range of -48μA~22μA, and the relative error within±3%. The output dynamic range of 14.1dB, and linearity error less than ±0.3dB. Four-segment CMOS quadratic polynomial circuit utilize Taylor to fitting sigmoid function. The circuit is designed by four sets of quadratic polynomial circuit and three sets of segmentation control circuit. The imitative result based on the range of -277μA~480μA,and the relative error within±3%. The PSRR are 34.3. The imitative tool is HSPICE and MATLAB. Circuit layout software used the CADANCE which provided with CIC and TSMC 0.35μm process.
 目錄中文摘要 ………………………………………………………………………………IAbstract ………………………………………………………………………II誌謝 …………………………………………………………………………………… III目錄 ……………………………………………………………………………………IV表目錄 ……………………………………………………………………………………V圖目錄 ………………………………………………………………………………VI 第一章 緒論………………………………………………………………………………1 1.1研究背景與動機…………………………………………………1 1.2論文結構………………………………………………………………2 第二章 二次多項式電路…………………………………………………………3 2.1平方電路公式推導……………………………………………3 2.2二次多項式公式推導………………………………………5 2.3二次多項式電路設計…………………………………………6 2.4定電流電路架構設計…………………………………………9第三章 最佳趨近法二次多項式電路設計與模擬……………………10 3.1前言………………………………………………………………………… 10 3.2最佳趨近法………………………………………………………………10 3.3最佳趨近法二次多項式電路設計………………………13 3.3.1 電路架構………………………………………………13 3.3.2 數學原理………………………………………………14 3.3.3 電路運作………………………………………………16 3.4模擬結果…………………………………………………………………18 3.5結論…………………………………………………………………………21第四章 四分段法二次多項式電路設計與模擬………………………22 4.1前言……………………………………………………………………………22 4.2分段控制電路……………………………………………………………22 4.3四分段法二次多項式電路設計……………………………26 4.3.1 電路架構…………………………………………………26 4.3.2 數學原理…………………………………………………29 4.3.3 電路運作…………………………………………………30 4.3.3.1正半部電路運作……………………30 4.3.3.2負半部電路運作……………………31 4.4模擬結果……………………………………………………………………32 4.5結論……………………………………………………………………………36第五章 電路晶片設計……………………………………………………………………37 5.1設計考量……………………………………………………………………37 5.2電路佈局圖…………………………………………………………………38 5.3最佳趨近法二次多項式電路晶片設計與模擬……40 5.4二分段法二次多項式電路晶片設計與模擬………45第六章 總結與未來展望…………………………………………………………………50參考文獻 …………………………………………………………………………………51
 [1] K. J. Lin, “Two-Quadrant CMOS Plug-in Divider,” IEICE Trans. Fundamentals., Vol.E91-A, No. 9, pp. 2682-2684, Sep. 2008.[2] K. J. Lin, “CMOS Current-Mode Companding Divider,” IEICE Trans. Electron., Vol.E92-C, No. 3, pp. 380-382, Mar. 2009.[3] K. J. Lin, “Two-Quadrant Compact CMOS Current Divider,” IEICE Trans. Fundamentals., Vol.E92-A, No. 7, pp. 1713-1715, Jul. 2009.[4] K. J. Lin and C.C.Jen, “CMOS Nth-Switchable-Root Circuit,” IEICE Trans. Electron., Vol.E93-C, No. 1, Jan.2010[5] K. J. Lin and C.C.Jen, “CMOS Current-Mode Geometric-Mean Circuit with N input,” IEEE International Symposium on signal, Circuit &; Systems, Iasi, Romania,pp. 1-4, Jul. 9-10,2009.[6] A.Vindran, E.Vidal , and M. Ismail, “Compact Low Voltage Four Quadrant COMS Current Multiplier,” Electronics Letters IET Journals, Vol.37, No.24,pp. 1428-1429,Nov.2001.[7] M.Lopez and A. Carlosena, “Current-Mode Multiplier/Divider Circuit Based on the MOS Translinear Principle,” Analog Integrated Circuits and signal Processing, Vol.29,pp. 256-278,2004.[8] K. J. Lin and C.C.Jen, “CMOS current-mode geometric-mean circuit with n input,” IEEE CONFERENCES , pp.1-4,2009.[9] D.Q.Hoang , T.K.Nguyen, and L.S.Gug, “CMOS Exponential Current to Voltage Circuit Based on Newly Proposed Approximation Method, ” ISCAS-IEEE 2004, Vol.2,pp.865-8,2004.[10] Q. S.Ru, Y.Yang, Z.Q.Ning, and T.Song, Shanghai, China, “The Application of Nerve Net Algorithm to Reduce Vehicle Weigh in Motion System Error,” IEEE Conference Publications, Vol.2, pp.511-514,2010.[11] J.Garg , M.Arik ,and E.Tkaczyk , “Methodology for computation and measurement of thermal conductivity for thin film composite substrates,” IEEE Conference Publications,Vol.1,pp.102-107,2004.[12] K.Bult and H.Wallinga, “A class of analog CMOS circuits based on the square-law characteristic of an MOS transistor in saturation,” IEEE Journal ,Vol.22,pp.357-365,Jun 1987.[13] W.Liu , S.I.Liu , and S. K.Wei, “Cmos differential-mode exponentialvoltage-to-current converter ,” Analog Integrated Circuitsand Signal Processing 45 (2005), 163–168.[14] M.Kumngern , J Chanwutitum and K.Dejhan, “Simple cmos current-mode exponential function generator circuit,” Proceedings of ECTI-CON, Krabi, 709–712, 2008.[15] V.Kalenteridis , S.Vlassis , and S.Siskos, “A cmos linear-in-db vga based on exponential current generator,” 6th International Conference on Design &; Technology of Integrated Systems in Nanoscale Era, Athens,2011.[16] K. Golnar, M. Mitra , and A. Majid, “Analog Implementation of a NovelResistive-Type Sigmoidal Neuron,” IEEE Transactions on very large scale integration (VLSI) systems, Vol.20, NO. 4 , April.2012.[17] M.Taher, A.Shwehneh, “A Reconfigurable Satlin/Sigmoid/Gaussian/Triangular Basis Functions Computation Circuit,” IEEE Conference publication , pp.1172-1175,2006.[18] C.Lu, B.Shi , and L.Chen, “Hardware Implementation of an On-chip BP Learning Neural Network with Programmable Neuron Characteristics and Learning Rate Adaptation,” IEEE Conference publication ,Vol.1,pp.212-215,2001.
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