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研究生:吳培綸
研究生(外文):Pei-Lun Wu
論文名稱:利用最佳趨近法及四分段法設計之CMOS 二次多項式電路
論文名稱(外文):Design of CMOS Quadratic Polynomial Circuit Using Best Fit Method and Four-Segment Method
指導教授:林國珍
指導教授(外文):Kuo-Jen Lin
學位類別:碩士
校院名稱:中華大學
系所名稱:電機工程學系碩士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2012
畢業學年度:100
語文別:中文
論文頁數:52
中文關鍵詞:最佳趨近法二次多項式sigmoid函數
外文關鍵詞:Best FitQuadratic FunctionSigmoid Function
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本論文利用最佳趨近法及四分段法設計CMOS二次多項式電路。以電流模式下的CMOS二次多項式電路為基礎,依照使用者所需的精準度來調整電路組成與MOS電晶體的長寬比值。
本論文從平方電路開始介紹,由平方電路衍生出二次多項式電路,進而設計出最佳趨近法CMOS二次多項式電路與四段設計CMOS二次多項式電路。其中最佳趨近法CMOS二次多項式電路的設計是以指數函數為例來實現電路,模擬結果為輸入範圍介於-48μA至21μA,輸出相對誤差±3%以內,其線性度在±0.3dB以內達14.1dB。
四分段法CMOS二次多項式電路的設計使用泰勒二次多項式電路來近似sigmoid函數,以四組二次多項式電路加上三組分段控制電路,完成電路設計。其模擬結果在輸入範圍為-277μA至480μA,輸出相對誤差±3%以內,PSRR值為34.3。
模擬工具使用有HSPICE與MATLAB等。電路佈局軟體使用國家晶片中心(CIC)提供的CADANCE及台積電(TSMC)0.35製程。

In this thesis, we design CMOS quadratic polynomial circuit using best fit method and four-segment method. The propose of this thesis is based on CMOS current-mode quadratic function circuits, its W/L ratio and construction could be adjusted by the relative error that the users needed.
First we explain how to implement CMOS current-mode quadratic circuits and design the proposed circuit in the way of multiple corrections. We use the best fit CMOS quadratic polynomial circuit to realization exponential function. The imitative result based on the range of -48μA~22μA, and the relative error within±3%. The output dynamic range of 14.1dB, and linearity error less than ±0.3dB.
Four-segment CMOS quadratic polynomial circuit utilize Taylor to fitting sigmoid function. The circuit is designed by four sets of quadratic polynomial circuit and three sets of segmentation control circuit. The imitative result based on the range of -277μA~480μA,
and the relative error within±3%. The PSRR are 34.3.
The imitative tool is HSPICE and MATLAB. Circuit layout software used the CADANCE which provided with CIC and TSMC 0.35μm process.

目錄
中文摘要 ………………………………………………………………………………I
Abstract ………………………………………………………………………II
誌謝 …………………………………………………………………………………… III
目錄 ……………………………………………………………………………………IV
表目錄 ……………………………………………………………………………………V
圖目錄 ………………………………………………………………………………VI

第一章 緒論………………………………………………………………………………1
1.1研究背景與動機…………………………………………………1
1.2論文結構………………………………………………………………2
第二章 二次多項式電路…………………………………………………………3
2.1平方電路公式推導……………………………………………3
2.2二次多項式公式推導………………………………………5
2.3二次多項式電路設計…………………………………………6
2.4定電流電路架構設計…………………………………………9
第三章 最佳趨近法二次多項式電路設計與模擬……………………10
3.1前言………………………………………………………………………… 10
3.2最佳趨近法………………………………………………………………10
3.3最佳趨近法二次多項式電路設計………………………13
3.3.1 電路架構………………………………………………13
3.3.2 數學原理………………………………………………14
3.3.3 電路運作………………………………………………16
3.4模擬結果…………………………………………………………………18
3.5結論…………………………………………………………………………21

第四章 四分段法二次多項式電路設計與模擬………………………22
4.1前言……………………………………………………………………………22
4.2分段控制電路……………………………………………………………22
4.3四分段法二次多項式電路設計……………………………26
4.3.1 電路架構…………………………………………………26
4.3.2 數學原理…………………………………………………29
4.3.3 電路運作…………………………………………………30
4.3.3.1正半部電路運作……………………30
4.3.3.2負半部電路運作……………………31
4.4模擬結果……………………………………………………………………32
4.5結論……………………………………………………………………………36
第五章 電路晶片設計……………………………………………………………………37
5.1設計考量……………………………………………………………………37
5.2電路佈局圖…………………………………………………………………38
5.3最佳趨近法二次多項式電路晶片設計與模擬……40
5.4二分段法二次多項式電路晶片設計與模擬………45
第六章 總結與未來展望…………………………………………………………………50
參考文獻 …………………………………………………………………………………51

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[2] K. J. Lin, “CMOS Current-Mode Companding Divider,” IEICE Trans. Electron., Vol.E92-C, No. 3, pp. 380-382, Mar. 2009.
[3] K. J. Lin, “Two-Quadrant Compact CMOS Current Divider,” IEICE Trans. Fundamentals., Vol.E92-A, No. 7, pp. 1713-1715, Jul. 2009.
[4] K. J. Lin and C.C.Jen, “CMOS Nth-Switchable-Root Circuit,” IEICE Trans. Electron., Vol.E93-C, No. 1, Jan.2010
[5] K. J. Lin and C.C.Jen, “CMOS Current-Mode Geometric-Mean Circuit with N input,” IEEE International Symposium on signal, Circuit &; Systems, Iasi, Romania,
pp. 1-4, Jul. 9-10,2009.
[6] A.Vindran, E.Vidal , and M. Ismail, “Compact Low Voltage Four Quadrant COMS Current Multiplier,” Electronics Letters IET Journals, Vol.37, No.24,pp. 1428-1429,Nov.
2001.
[7] M.Lopez and A. Carlosena, “Current-Mode Multiplier/Divider Circuit Based on the MOS Translinear Principle,” Analog Integrated Circuits and signal Processing, Vol.29,pp. 256-278,2004.
[8] K. J. Lin and C.C.Jen, “CMOS current-mode geometric-mean circuit with n input,” IEEE CONFERENCES , pp.1-4,2009.
[9] D.Q.Hoang , T.K.Nguyen, and L.S.Gug, “CMOS Exponential Current to Voltage Circuit Based on Newly Proposed Approximation Method, ” ISCAS-IEEE 2004, Vol.2,pp.865-8,2004.

[10] Q. S.Ru, Y.Yang, Z.Q.Ning, and T.Song, Shanghai, China, “The Application of Nerve Net Algorithm to Reduce Vehicle Weigh in Motion System Error,” IEEE Conference Publications, Vol.2, pp.511-514,2010.
[11] J.Garg , M.Arik ,and E.Tkaczyk , “Methodology for computation and measurement of thermal conductivity for thin film composite substrates,” IEEE Conference Publications,Vol.1,pp.102-107,2004.
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[14] M.Kumngern , J Chanwutitum and K.Dejhan, “Simple cmos current-mode exponential function generator circuit,” Proceedings of ECTI-CON, Krabi, 709–712, 2008.
[15] V.Kalenteridis , S.Vlassis , and S.Siskos, “A cmos linear-in-db vga based on exponential current generator,” 6th International Conference on Design &; Technology of Integrated Systems in Nanoscale Era, Athens,2011.
[16] K. Golnar, M. Mitra , and A. Majid, “Analog Implementation of a Novel
Resistive-Type Sigmoidal Neuron,” IEEE Transactions on very large scale integration (VLSI) systems, Vol.20, NO. 4 , April.2012.
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