臺灣博碩士論文加值系統

本文呈現兩種新架構，分別稱為摺疊R-2R階梯式電流導引數位類比轉換器與虛擬二進位摺疊R-2R階梯式電流導引數位類比轉換器。並且針對R-2R階梯式電流導引數位類比轉換器、摺疊R-2R階梯式電流導引數位類比轉換器與虛擬二進位摺疊R-2R階梯式電流導引數位類比轉換器進行非線性度的學理分析，分析過程同時考慮電流非匹配度與電阻非匹配度的影響。
本文也針對虛擬二進位摺疊R-2R階梯式電流導引DAC提出一套設計流程，使設計者可快速且精準選擇電路中電阻與電流源各自所需的元件非匹配度。以DAC解析度操作於6位元為例，本作品相較於傳統R-2R階梯式電流導引DAC可節省56.25%的電阻使用量，以及減少56.25%的功率消耗。以TSMC 0.18um 1P6M製程所製造的晶片核心面積為0.042mm2，量測結果顯示DNL與INL分別為0.34LSB與0.25LSB，最大靜態功率消耗為8mW。

This thesis presents two new architectures which are called folded R-2R ladder-based current-steering digital to analog converter and pseudo binary folded R-2R ladder-based current-steering digital to analog converter, respectively. A theoretical nonlinearity analysis of R-2R ladder-based current-steering digital to analog converter and proposed circuits is presented. In addition, the nonlinearities caused by the current mismatches and the resistor mismatches are also analyzed.
This thesis also presents a design flow of pseudo binary folded R-2R ladder-based current-steering digital to analog converter. The derived equations enable circuit designers to quickly select the most suitable design for their applications by calculating the required resistor mismatch and required current mismatch. In the case of 6-bit resolution, the proposed circuit can reduce the total number of required unit resistors by up to 56.25% and 56.25% power consumption compared with conventional R-2R ladder-based current-steering DAC. The measured DNL and INL are 0.34LSB and 0.25LSB, respectively. The converter consumes 8mW with 1.8V power supply. The active area of chip is less than 0.042mm2 in TSMC 0.18um 1P6M process.

目錄
中文摘要 I
英文摘要 II
誌謝 III
目錄 IV
圖目錄 VIII
表目錄 XI
1 緒論 1
1.1 研究背景 1
1.2 研究動機 2
1.3 章節介紹 3
2 數位類比轉換器基本原理 4
2.1 簡介 4
2.2 靜態特性 5
2.2.1 微分非線性誤差 5
2.2.2 積分非線性誤差 5
2.2.3 增益誤差 6
2.2.4 偏移誤差 6
2.3 動態特性 7
2.3.1 訊號雜訊比 7
2.3.2 無突波動態範圍 7
2.4 電流導引數位類比轉換器架構介紹 8
2.4.1 二進位權值電流導引數位類比轉換器 8
2.4.2 單位權值電流導引數位類比轉換器 10
2.4.3 分割式電流導引數位類比轉換器 11
2.5 R-2R階梯數位類比轉換器 12
3 R-2R階梯式電流導引數位類比轉換器之非線性度分析 14
3.1 架構介紹 14
3.2 輸出電壓通式推導 15
3.3 微分非線性度與差分非線性度之最差狀況分析 20
3.4 微分非線性度分析 21
3.4.1 電流誤差分析 22
3.4.2 電阻誤差分析 23
3.4.3 所有元件誤差分析 25
3.5 以理想參考線為分析基礎之積分非線性度分析 26
3.5.1 電流誤差分析 27
3.5.2 電阻誤差分析 27
3.5.3 所有元件誤差分析 28
3.6 以起迄點參考線為分析基礎之積分非線性度分析 29
3.6.1 電流誤差分析 29
3.6.2 電阻誤差分析 30
3.6.3 所有元件誤差分析 32
3.7 DNL分析與INL分析之比較 33
3.8 DNL分析與INL分析之驗證 35
4 摺疊R-2R階梯式電流導引數位類比轉換器之非線性度分析 37
4.1 架構介紹 37
4.2 輸出電壓通式推導 38
4.3 微分非線性度與差分非線性度之最差狀況分析 42
4.4 微分非線性度分析 43
4.4.1 電流誤差分析 44
4.4.2 電阻誤差分析 46
4.4.3 所有元件誤差分析 47
4.5 以理想參考線為分析基礎之積分非線性度分析 48
4.5.1 電流誤差分析 49
4.5.2 電阻誤差分析 50
4.5.3 所有元件誤差分析 50
4.6 以起迄點參考線為分析基礎之積分非線性度分析 51
4.6.1 電流誤差分析 52
4.6.2 電阻誤差分析 53
4.6.3 所有元件誤差分析 54
4.7 DNL分析與INL分析之比較 55
4.8 DNL分析與INL分析之驗證 57
5 虛擬二進位摺疊R-2R階梯式電流導引數位類比轉換器之非線性度分析 60
5.1 架構介紹 60
5.2 輸出電壓通式推導 61
5.3 微分非線性度分析 65
5.3.1 電流誤差分析 67
5.3.2 電阻誤差分析 68
5.3.3 所有元件誤差分析 69
5.4 積分非線性度分析 70
5.4.1 電流誤差分析 71
5.4.2 電阻誤差分析 72
5.4.3 所有元件誤差分析 72
5.5 DNL分析與INL分析之比較 73
5.6 DNL分析與INL分析之驗證 75
6 設計流程與晶片實測 77
6.1 架構選擇 77
6.2 設計流程 79
6.3 晶片模擬 82
6.4 晶片實測 84
7 結論與未來展望 88
7.1 結論 88
7.2 未來展望 88
參考文獻 89

圖目錄
圖2-1 N位元DAC示意圖 4
圖2-2 N位元DAC之理想轉換曲線 5
圖2-3 3位元DAC之增益誤差示意圖 6
圖2-4 3位元DAC之偏移誤差示意圖 7
圖2-5 二進位權值電流導引DAC 9
圖2-6 單位權值電流導引DAC 10
圖2-7 分割式電流導引DAC 12
圖2-8 電壓模式R-2R LADDER DAC 12
圖2-9 電流模式R-2R LADDER DAC 13
圖3-1 N位元R-2R LADDER-BASED電流導引DAC 15
圖3-2 具有電流誤差與電阻誤差之R-2R LADDER-BASED電流導引DAC 15
圖3-3 DNL統計分析曲線 20
圖3-4 INL統計分析曲線 20
圖3-5 不同解析度之電流非匹配度要求 33
圖3-6 不同解析度之電阻非匹配度要求 34
圖3-7 不同解析度之所有元件非匹配度要求 35
圖3-8 以所有元件所需非匹配度分析之DNL 35
圖3-9 以所有元件所需非匹配度分析之INLIDEAL 36
圖3-10 以所有元件所需非匹配度分析之INLEND-POINT 36
圖4-1 摺疊R-2R LADDER-BASED電流導引DAC 37
圖4-2 具有電流誤差與電阻誤差之摺疊R-2R LADDER-BASED電流導引DAC 38
圖4-3 DNL統計分析曲線 43
圖4-4 INL統計分析曲線 43
圖4-5 不同解析度之電流非匹配度要求 56
圖4-6 不同解析度之電阻非匹配度要求 56
圖4-7 不同解析度之所有元件非匹配度要求 57
圖4-8 以所有元件所需非匹配度分析之DNL 58
圖4-9 以所有元件所需非匹配度分析之INLIDEAL 58
圖4-10 以所有元件所需非匹配度分析之INLEND-POINT 59
圖5-1 虛擬二進位摺疊R-2R LADDER-BASED電流導引DAC 60
圖5-2 具有電流誤差與電阻誤差之虛擬二進位摺疊R-2R LADDER-BASED電流導引DAC 61
圖5-3 不同解析度之電流非匹配度要求 73
圖5-4 不同解析度之電阻非匹配度要求 74
圖5-5 不同解析度之所有元件非匹配度要求 74
圖5-6 以所有元件所需非匹配度分析之DNL 75
圖5-7 以所有元件所需非匹配度分析之INLIDEAL 76
圖6-1 6位元R-2R LADDER-BASED電流導引DAC 77
圖6-2 6位元摺疊R-2R LADDER-BASED電流導引DAC 78
圖6-3 6位元虛擬二進位摺疊R-2R LADDER-BASED電流導引DAC 78
圖6-4 不同解析度之電流非匹配度與電阻非匹配度曲線圖 80
圖6-5 差動輸出之疊接式電流鏡 81
圖6-6 DNL模擬結果 82
圖6-7 INL模擬結果 82
圖6-8 SFDR之模擬結果 83
圖6-9 靜態特性量測系統示意圖 84
圖6-10 動態特性量測系統示意圖 84
圖6-11 DNL量測結果 85
圖6-12 INL量測結果 85
圖6-13 SFDR量測結果 86
圖6-14 6位元虛擬二進位摺疊R-2R LADDER-BASED電流導引DAC晶片圖 87

表目錄
表3-1 4位元R-2R LADDER-BASED電流導引DAC之誤差電阻值於輸出電壓貢獻表 18
表3-2 5位元R-2R LADDER-BASED電流導引DAC之誤差值電阻於輸出電壓貢獻表 18
表4-1 6位元摺疊R-2R LADDER-BASED電流導引DAC之誤差電阻值於輸出電壓貢獻表 40
表4-2 8位元摺疊R-2R LADDER-BASED電流導引DAC之誤差電阻值於輸出電壓貢獻表 41
表5-1 6位元虛擬二進位摺疊R-2R LADDER-BASED電流導引DAC之誤差電阻值於輸出電壓貢獻表 63
表5-2 8位元虛擬二進位摺疊R-2R LADDER-BASED電流導引DAC之誤差電阻值於輸出電壓貢獻表 64
表6-1 三種6位元R-2R LADDER-BASED電流導引DAC之電路規格比較表 79
表6-2 虛擬二進位摺疊R-2R LADDER-BASED電流導引DAC模擬規格表 83
表6-3 虛擬二進位摺疊R-2R LADDER-BASED電流導引DAC實測規格表 87

[1]C. H. Tsai, J. H. Wang, H. Y. Zheng, C. T. Chang, and C. Y. Wang, “A new compact low-offset push–pull output buffer with current positive feedback for a 10-bit LCD source driver,” IET Circuits, Devices &; Systems, vol. 4, no. 6, pp. 539-547, 2010.
[2]J. K. Woo, D. Y. Shin, D. K. Jeong, and S. K, “High-speed 10-bit LCD column driver with a split DAC and a class-AB output buffer,” IEEE Trans. Consumer Electronics, vol. 55, no. 3, pp. 1431-1438, Aug. 2009.
[3]C. C. Chen, N. K. Lu, C. H. Hsu, and M. L. Lee, “Color-depth improvement using gamma voltage control,” in Proc. SID Symp. Dig., 2006, pp. 351–354.
[4]Y. Perelman and R. Ginosar, “A Low-Power Inverted Ladder D/A Converter,” IEEE Trans. Circuits and Systems II: Express Briefs, vol. 53, No. 6, pp. 497-501, Jun. 2006.
[5]C. C. Chen, N. K. Lu, and Y. Z. Zeng, “Nonlinearity analysis of folded Multi-LSB decided resistor string digital to analog converter,” Analog Integrated Circuits and Signal Processing, vol. 70, no. 3, pp. 357-367. Mar. 2012.
[6]H. S. Kim, J. Y. Jeon, S. W. Lee, J. H. Yang, S. T. Ryu, and G. H. Cho, “A 0.014mm2 9b switched-current DAC for AMOLED mobile display drivers,” in Proc. IEEE Int. Solid State Circuits Conf. (ISSCC), 2011, pp. 316-317.
[7]D. Raiteri, F. Torricelli, K. Myny, M. Nag, B. V. D. Putten, E. Smits, S. Steudel, K. Tempelaars, A. Tripathi, G. Gelinck, A. V. Roermund, and E. Cantatore, “A 6b 10MS/s Current-Steering DAC Manufactured with Amorphous Gallium-Indium-Zinc-Oxide TFTs Achieving SFDR > 30dB up to 300kHz,” in Proc. IEEE Int. Solid State Circuits Conf. (ISSCC), 2012, pp. 314-315.
[8]W. H. Tseng, C. W. Fan, and J. T. Wu, “A 12b 1.25GS/s DAC in 90nm CMOS with >70dB SFDR up to 500MHz,” in Proc. IEEE Int. Solid State Circuits Conf. (ISSCC), 2011, pp. 192-193.
[9]X. Wu, P. Palmers, and M. S. J. Steyaert, “A 130 nm CMOS 6-bit full nyquist 3 GS/s DAC,” IEEE J. Solid-State Circuit, vol.43, no. 11, pp.2396-2403, Nov. 2008.
[10]R. L. Chen and S. J. Chang, “A 5-bit 1.35-GSPS DAC for UWB transceivers,” in Proc. IEEE Int. Conf. Ultra-Wideband (ICUWB), 2009, pp. 175-179.
[11]J. Jung, K. H. Baek, S. I. Lim, S. Kim, and S. M. Kang, “Design of a 6 bit 1.25 GS/s DAC for WPAN,” in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), 2008, pp. 2262-2265.
[12]S. M. Lin, D. U. Li and W. T. Chen, “1 V 1.25 GS/s 8 mW D/A converters for MB-OFDM UWB transceivers,” in Proc. IEEE Int. Conf. Ultra-Wideband (ICUWB), 2007, pp. 453-456.
[13]J. J. Jung, B. h. Park, S. S. Choi, S. I. Lim, and S. Kim, “A 6-bit 2.704Gsps DAC for DS-CDMA UWB,” in Proc. IEEE Asia Pacific Conf. Circuits and Systems (APCCAS), 2006, pp. 347-350.
[14]A. van den Bosch, M. Borremans, M. Steyaert, and W. Sansen, “A 10-bit 1-GSample/s Nyquist current-steering CMOS D/A converter,” IEEE J. Solid-State Circuit, vol.36, no. 3, pp.315-324, Mar. 2001.
[15]IEEE Trial-Use Standard for Digitizing Waveform Recorders, IEEE standard 1057, 1989.
[16]R. J. Baker, CMOS circuit design, layout, and simulation. Third Edition, New York: IEEE Press, 2010.
[17]B. Razavi, Principles of data conversion system design. New York: IEEE Press, 1995.
[18]D. Marche and Y. Savaria, “Modeling R-2R segmented ladder DACs,” IEEE Trans. Circuits and Systems I: Regular Paper, vol. 57, no. 1, pp. 31–43, Jan. 2010.
[19]D. Marche, Y. Savaria, and Y. Gagnon, “An improved switch compensation technique for inverted R-2R ladder DACs,” IEEE Trans. Circuits and Systems I: Regular Paper, vol. 56, no. 6, pp. 1115–1124, Jun. 2009.
[20]D. Marche, Y. Savaria, and Y. Gagnon, “Laser fine-tuneable deep-submicrometer CMOS 14-bit DAC,” IEEE Trans. Circuits and Systems I: Regular Paper, vol. 55, no. 8, pp. 2157–2165, Sep. 2008.
[21]Y. Lin and R. Geiger, “Resistors layout for enhancing yield of R-2R DACs,” in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), 2002, pp. v-97 – v-100.
[22]L. Wang, Y. Fukatsu, and K. Wakanabe, “Characterization of current-mode CMOS R-2R ladder digital-to-analog converters,” IEEE Trans. Instrumentation and Measurement, vol. 50, no. 6, pp. 1781-1786, Dec. 2001.
[23]T. C. Lee and C. H. Lin, “Nonlinear R-2R transistor-only DAC,” IEEE Trans. Circuits and Systems I: Regular Paper, vol. 57, no. 10, pp. 2644–2653, Jun. 2010.
[24]S. Halder, H. Gustat, C. Scheytt, and A. Thiede, “A 20GS/s 8-Bit Current Steering DAC in 0.25μm SiGe BiCMOS Technology,” in Proc. European Microwave Integrated Circuit Conference(EuMIC), 2008, pp. 147-150.
[25]B. Nejati and L. Larson, “Power/Area trade-offs in low-power/low-area unary-R-2R CMOS digital-to-analog converters,” in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), 2007, pp. 1473-1476.
[26]B. Nejati and L. Larson, “An area optimized 2.5-V 10-b 200-MS/s 200-μA CMOS DAC,” in Proc. IEEE Custom Integrated Circuits Conf. (CICC), 2006, pp. 161-164.
[27]S. Kazeminia, Y. Hesamiafshar, K. Hadidi, and A. Khoei, “On matching properties of R-2R ladders in high performance digital-to-analog converters,” in Proc. Iranian Conf. Electrical Engineering (ICEE), 2010, pp. 432-436.
[28]Roy D Yates and David J Goodman, Probability and Stochastic Processes: A Friendly Introduction for Electrical and Computer Engineers. Second Edition, Wiley, 2005.
[29]N. K. Lu, C. C. Chen, K. Y. Lin, and Y. Z. Zeng, “Folded R-2R ladder current-steering digital to analog converter,” U.S. Patent 7 646 322, Jan. 12, 2010.