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研究生:鄭威佑
研究生(外文):Cheng, Wei-Yu
論文名稱:以整數線性規劃法解決3D超大型積體電路增量式平面規劃
論文名稱(外文):An Integer Linear Programming Approach to 3D VLSI Incremental Floorplanning
指導教授:程仲勝程仲勝引用關係
指導教授(外文):Cherng, Jong-Sheng
口試委員:林浩仁王欣平程仲勝
口試委員(外文):Lin, How-RernWang, Shin-PingCherng, Jong-Sheng
口試日期:2012-07-16
學位類別:碩士
校院名稱:大葉大學
系所名稱:資訊工程學系碩士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2012
畢業學年度:100
語文別:中文
論文頁數:106
中文關鍵詞:3D IC增量式平面規劃整數線性規劃
外文關鍵詞:3D ICIncremental FloorplanningInteger Linear programming
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積體電路設計已進入高效能、低功率、高密度以及異質整合的時代,傳統2D IC設計漸漸地已無法滿足現今IC產品之需求,因此IC設計朝向三維方式發展已是目前克服設計困難度最有效方式之一。
3D IC平面規劃雖然可以改善電路連線延遲的問題,但因電路系統設計日趨複雜,難以設計出一個面積、時序、功率和線長都最佳的佈局結果,因此很可能需反覆執行電路平面規劃,以求得一個較佳的結果,但這會導致後端實體設計所需的時間增加。為了縮短重複進行平面規劃的時間,增量式平面規劃(incremental floorplanning)策略已被提出用以改進先前所得之平面規劃中當某些模組位置、維度修改或少數模組間相對位置改變後,不論其修改範圍大或少,皆必須耗時地整個重新執行平面規劃之缺點。
綜上所述,所提論文的研究方向是設計一個適用於3D IC之增量式平面規劃系統,嘗試達到佈局最佳化以保障系統效能為目標。在本論文中,我們嘗試以數學規劃法(mathematical programming)發展增量式平面規劃。首先依據原始平面圖找出欲增量模組與其周圍模組間的閒置空間大小,及分析可增量之範圍,並在不改變模組間拓撲關係及不增加整體晶片面積之條件下,找出最佳模組增量後之佈局結果。以上作法以整數線性規劃(integer linear programming)加以實現,並以LINGO軟體求解。實驗顯示提出的增量式平面規劃系統可有效將模組增量,並改善繞線延遲問題。
The current integrated circuit design trend is towards high performance, low power, high density as well as heterogeneous integration. Traditional two-dimensional integrated circuit (2D IC) design has been unable to meet nowadays need of IC product. Hence, three-dimensional integrated circuit (3D IC) is emerging as an effective way for overcoming the barriers in 2D IC design.
Though interconnection delay can been improved by 3D IC floorplanning, circuits are growing in complexity, so it is difficult to design an optimal layout solution. Therefore, to obtain a better result, it needs performing floorplanning repeatedly. However, the process will increase the time of physical design. To reduce the time of floorplanning, incremental floorplanning has been proposed to deal with local or incremental change of layout solution efficiently.
To sum up, an incremental floorplanning system has beeb proposed for 3D ICs to guide 3D physical design towards an optimal layout solution in this thesis, and it has been developed based on mathematical programming. In the first of the procedure, the changed modules and whitespace around them are found in the original floorplan, and then the final layout is obtained without the change of topology among modules and without the increase of chip size. The whole procedure has been implemented by integer linear programming method and been solved by LINGO software. Experimental results show that it is effective for this incremental floorplanning system to change modules and improve interconnection delay problem.
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簽名頁
摘要 iii
ABSTRACT iv
誌謝 v
目錄 vi
圖目錄 viii
表目錄 xi
第一章 緒論 1
1.1 研究動機與目的 1
1.2 研究方法 2
1.3 論文架構 3
第二章 相關文獻探討 4
2.1 3D晶片技術整合 4
2.1.1 封裝堆疊 4
2.1.2 晶片堆疊 6
2.1.3 TSV堆疊 7
2.1.4 3D IC堆疊方式 8
2.2 增量式平面規劃 11
2.2.1 增量式實體設計 11
2.2.2 植基於基因演算法之增量式平面規劃 12
2.2.3 植基於CBL表示法之增量式平面規劃 13
2.2.4 植基於模擬退火演算法之增量式平面規劃 16
2.2.5 植基於Delaunay Triangulation表示法之增量式平面規劃 20
2.2.6 植基於Corner Stitching表示法之增量式平面規劃 21
2.3 線性規劃 24
第三章 整數線性規劃法解決3D VLSI增量式平面規劃 25
3.1 問題描述 25
3.2 整數線性規劃 25
3.2.1 位移限制 28
3.2.2 水平垂直限制 29
3.2.3 邊界擴展限制 30
3.2.4 增量面積限制 32
3.2.5 寬高限制 33
3.2.6 繞線長度限制 34
3.2.7 TSV位置限制 38
第四章 實驗結果 45
4.1 兩層模組增量 46
4.2 兩層模組增量減量 54
4.3 三層模組增量減量 61
第五章結論與未來展望 67
參考文獻 68
附錄 71
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[2] 郭子熒,3D IC技術簡介與其發展現況,先進微系統與構裝技術聯盟季刊,第三十期,2008年06月,78~85頁。
[3] 游淑惠,台灣半導體發展新紀元– 3D IC,系統晶片第9期,2008年,3~10頁。
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[7] M. Kawano, S. Uchiyama, Y. Egawa, N. Takahashi, Y. Kurita, K. Soejima, M. Komuro, S. Matsui, K. Shibata, J. Yamada, M. Ishino, H. Ikeda, Y. Saeki, O. Kato, H. Kikuchi and T.
Mitsuhashi, “A 3D Packaging Technology for 4 Gbit Stacked DRAM with 3 Gbps Data Transfer”, IEDM, Shimokuzawa, Sagamihara, Kanagawa, Japan, 2006.
[8] P. D. Franzon, W. R. Davis, M. B. Steer, S. Lipa, E. C. Oh, T. Thorolfsson, S. Melamed, S. Luniya, T. Doxsee, S. Berkeley, B. Shani and K. Obermiller, “Design and CAD for 3D Integrated Circuits”, DAC, Anaheim, California, USA, June 2008.
[9] I. Loi, S. Mitra, T. H. Lee, S. Fujita and Luca Benini,“A Low-overhead Fault Tolerance Scheme for TSV-based 3D Network on Chip Links”, ICCAD, Toshiba, San Jose, CA, USA, 2008.
[10] Amkor Technology:http://www.amkor.com/.
[11] D. H. Kim, K. Athikulwongse, and S. K. Lim, “A Study of Through-Silicon-Via Impact on the 3D Stacked IC Layout”, ICCAD’09, San Jose, California, USA, November 2-5 2009.
[12] J. Cong and M. Sarrafzadeh “Incremental Physical Design” Proceedings of International Symposium on Physical Design. 2000.
[13] Y. Liu, H. Yang and R. Luo “An Incremental Floorplanner Based on Genetic Algorithm” Proceedings of 5th International Conference on ASCI Vol.1, 2003, Pages 331-334.
[14] L. Yang, Y. Ma, X. Hong, S. Dong and Q. Zhou “An Incremental Algorithm for Non-Slicing Floorplan Based on Corner Block List Representation” Chinese Journal of Semiconductors Vol.26
No.12, 2005, Pages 2335-2343.
[15] 高一宏、程仲勝,“植基於Corner Block List表示法之增量式平面規劃之研究” 私立大葉大學電機工程研究所,2007。
[16] Qing. Dong, Bo. Yang, Jing. Li, “Incremental Buffer Insertion and Module Resizing Algorithm Using Geometric Prograμming” Great Lakes Symposium on VLSI, 2009, Pages 413-416.
[17] 張家銘、程仲勝,“植基於Corner Stitching表示法之增量式平面規劃之研究” 私立大葉大學電機工程研究所,2007。
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