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研究生:黃玟賢
研究生(外文):Huang, Wen-Shian
論文名稱:同時考量佈局面積與TSV線長的3D IC 之TSV擺置方法設計
論文名稱(外文):Simultaneously Considering Layout Area and TSV Wire Length on TSV Placement for 3D IC
指導教授:林浩仁林浩仁引用關係王欣平
指導教授(外文):Lin, How-RernWang, Shin-Peng
口試委員:林浩仁王欣平翁永昌林仁勇
口試委員(外文):Lin, How-RernWang, Shin-PengWong, Yung-ChangLin, Jen-Yung
口試日期:2012-07-16
學位類別:碩士
校院名稱:大葉大學
系所名稱:資訊工程學系碩士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2012
畢業學年度:100
語文別:中文
論文頁數:57
中文關鍵詞:3D IC矽穿孔擺置CMP平坦化3D晶片平坦化
外文關鍵詞:3D ICTSV placementCMP
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矽穿孔3D IC技術為將多個晶片堆疊,並使用矽穿孔(Through Silicon Vias;TSV)作為晶片間之訊號傳遞。矽穿孔3D IC 技術對於拉近晶片設計與製程技術的落差至為重要,由於使用3D堆疊,能使晶片面積縮小、提高訊號傳遞速度,並降低晶片功耗等效能,因此,矽穿孔3D IC技術日益重要。
然而,矽穿孔的孔徑較晶片晶元(Cell)與導線來的大,因此,會造成晶片佈局區域金屬密度大幅升高的現象,由於佈局的平坦度更加惡化,使得CMP研磨的挑戰更高,傳統2D IC的密度分析與虛擬金屬填充方法也不適用。
本文提出同時考量佈局面積與矽穿孔線長的3D IC矽穿孔擺置方法之設計,在佈局密度較低與密度差異較大的區域,進行矽穿孔安插;並考量與矽穿孔連線的元件位置來安插矽穿孔,可將原本繞線密度低的區域縮小密度差異,以解決密度差異過大而影響佈局的平坦度。矽穿孔擺置方式會分為密度最低與密度差異大兩種策略,由實驗結果可見本文所提出的方法,在佈局平坦度上能獲得良好的成效,且虛擬金屬添加量能有效的降低,其中密度差異大的擺置策略比密度最低的擺置策略,虛擬金屬添加量減少了4%-7.8%。若以矽穿孔連線長度而言,密度差異大的擺置策略的結果在線長多了2.11%-24%。

The semiconductor industry into the 3D IC technology and Through Silicon Vias (TSV) technology become increasingly important. On the same circuit design, 3D IC achieves high density, low power consumption and good timing slack. Chemical-Mechanical Polishing (CMP) technology is an important procedure in the fabrication of chip to enhance the overall smoothness need for increasing the yield. 3D IC technology will stack multiple chips using TSV as the components of the signal between the chip. But the TSV’s size is larger than the other functional cell, the metal density of the TSV region is extremely high. It’s a challenge to the traditional CMP planarization flow of 2D IC design.
In this paper, we proposed a TSV placement flow which takes chips density and TSV’s wire-length into account. The proposed method will consider the TSV’s wire-length, and place TSV in the layout of lower density to solve the density difference in the layout. Experimental results show that to placed TSV by the factor of density differences method increase the wire-length by 2.11%-24%, but can reduce the amount of dummy fills by 4%-7.8% compared with the placed TSV method according to lowest density.

封面內頁
簽名頁
中文摘要 iii
ABSTRACT iv
誌謝 v
目錄 vi
圖目錄 viii
表目錄 x

第一章 緒論 1
1.1 前言 1
1.2 CMP平坦化技術 4
1.3 研究動機 6
1.4 論文架構 7
第二章 文獻回顧 8
2.1 矽穿孔製程技術 8
2.2 矽穿孔耦合電容效應 10
2.3 3D IC良率問題 14
2.4 矽穿孔擺置 15
2.5 CMP平坦化技術與階梯式虛擬金屬填充法 18
第三章 同時考量佈局面積與TSV線長的3D IC之TSV擺置方法設計 21
3.1 問題描述 21
3.2 矽穿孔最小包圍矩形設置 24
3.3 矽穿孔擺置方法 25
3.4 考量密度差異大小與矽穿孔繞線長度擺置矽穿孔方法 31
第四章 實驗結果 33
4.1 實驗過程 33
4.2 實驗結果與分析 38
第五章 結論與未來展望 43
參考文獻 44

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