|
[1]Joint Video Team of ITU-T and ISO/IEC JTC 1, “Draft ITU-T Recommendation and Final Draft International Standard of Joint Video Specification (ITU-T Rec. H.264 ISO/IEC 14496-10 AVC),” Joint Video Team (JVT) of ISO/IEC MPEG and ITU-T VCEG, JVT-G050, Mar. 2003. [2]T. Wiegand, G. J. Sullivan, G. Bjontegaard, and A. Luthra, “Overview of the H.264/AVC video coding standard,” IEEE Transactions on Circuits and Systems for Video Technology., vol.13, no. 7, pp. 560-576, Jul. 2003. [3]P. List, A. Joch, J. Lainema, G. Bjøntegaard, and M. Karczewicz, “Adaptive deblocking filter,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 13, no. 7, pp. 614-619, Jul. 2003. [4]Bin Sheng, Wen Gao and Di Wu, “An implemented architecture of deblocking filter for H.264/AVC,” Proceedings of IEEE International Conference on Image Processing, vol. 1, pp. 665-668, Oct. 2004. [5]Yi-Chih Chao, Ji-Kun Lin; Jar-Ferr Yang, Bin-Da Liu, “A high throughput and data reuse architecture for H.264/AVC deblocking filter,” Proceedings of IEEE Asia and South Pacific Conference Circuits Systems, pp. 1260-1263, Dec. 2006. [6]Shen-Yu Shih, Cheng-Ru Chang, Youn-Long Lin, “A near optimal deblocking filter for H.264 advanced video coding, ” Proceedings of IEEE Asia and South Pacific Design Automation Conference, pp. 170–175, Jan. 2006. [7]Qing Chen, Wei Zheng, Jian Fang, Kai Luo, Bing Shi, Ming Zhang, Xianmin Zhang, “A pipelined hardware architecture of deblocking filter in H.264/AVC,” Proceedings of Third International Conference Communications and Network in China, pp. 815-819, 2008. [8]Chung-Ming Chen, Chung-Ho Chen, “Configurable VLSI architecture for deblocking filter in H.264/AVC,” IEEE Transactions on Very Large Scale Integration System, vol. 16, no. 8, pp. 1072–1082, Aug. 2008. [9]TOBAJAS F., CALLICO G.M., PEREZ P.A., ARMAS V., SARMIENTO R.: “An efficient double-filter hardware architecture for H.264/AVC deblocking filtering,” IEEE Transactions on Consumer Electronics, vol. 54, no. 1, pp. 131–139, Feb. 2008. [10]Cheng-An Chien, Hsiu-Cheng Chang, and Jiun-In Guo, “A High throughput In-Loop de-blocking filter supporting H.264/AVC BP/MP/HP video coding,” Proceedings of IEEE Asia Pacific Conference on Circuits and Systems, pp. 312-315, Nov. 2008. [11]Tsung-han Tsai, Yu-nan Pan, “High Efficient H.264/AVC Deblocking Filter Architecture for Real-time QFHD,” IEEE Transactions on Consumer Electronics , vol. 55, no. 4, pp. 2248-2256, Nov. 2009. [12]Xiaoliang Chen, Weiyi Xia, Xiaofeng Lu, “A High-throughput Low-power Hardware Architecture for H.264 Deblocking Filter,” Proceedings of 2010 2nd International Conference on Computer Engineering and Technology, vol. 2, pp. V2-561-V2-565, 2010. [13]Yuan-Chun Lin, Youn-Long Lin, “A two-result-per-cycle deblocking filter architecture for QFHD H.264/AVC decoder,” IEEE Transactions on Very Large Scale Integration System, vol. 17, no. 6, pp. 838-843, Jun. 2009. [14]K.-H. Chen, “48 Cycles-per-macro block deblocking filter accelerator for high-resolution H.264/AVC decoding,” Circuits, Devices & Systems, IET, vol. 4, iss. 3, pp. 196-206, Feb. 2010
|