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研究生:張哲銘
研究生(外文):Che -Ming
論文名稱:使用混和式濾波序列的高產能去區塊濾波器
論文名稱(外文):A High-throughput Debloking Filter With Hybrid Filtering Schedule
指導教授:陳德生陳德生引用關係
指導教授(外文):De-Sheng Chen
學位類別:碩士
校院名稱:逢甲大學
系所名稱:資訊工程所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2012
畢業學年度:100
語文別:中文
論文頁數:50
中文關鍵詞:去區塊濾波器濾波處理順序H.264/AVC
外文關鍵詞:Deblocking FilterFilter OrderH.264/AVC
相關次數:
  • 被引用被引用:0
  • 點閱點閱:130
  • 評分評分:
  • 下載下載:3
  • 收藏至我的研究室書目清單書目收藏:0
H.264/AVC 又稱 MPEG-4 第十部分,為目前常用之影像視訊壓縮標準,其壓縮率及視訊品質皆優於 MPEG-2/4。去區塊濾波器是用來改善視訊編解碼中採取區塊編碼所產生的區塊雜訊達到平滑的區塊邊緣讓畫面的品質提升。所以去區塊濾波器的最主要目的是提高解碼後的畫面品質。
在本文中,我們提出了一個新的濾波處理順序以及符合 H.264/AVC 視訊編碼標準的高產能去區塊濾波器硬體架構。建議的處理順序是精心安排的並行數據流,有效地提高處理速度和減少記憶體存取次數。在所提出的高產能去區塊濾波器硬體架構中提供最小延遲、最大生產量和內部記憶體資源的充分利用。並且達到 48 cycles/macroblock 生產量和 56 cycles/macroblock 的延遲。
H.264/AVC (Advanced Video Coding) or MPEG-4 Part 10 is commonly used video compression standard, compression rate and video quality are better than
MPEG – 2/4. A deblocking filter is a video filter applied to blocks in decoded video to improve visual quality and prediction performance by smoothing the sharp edges which can form between macroblocks when block coding techniques are used. The filter aims to improve the quality of decoded pictures.
In this paper, we propose a new processing order and a high-throughput hardware architecture for the deblocking filter operations in H.264/AVC video coding
standard. The proposed processing order is carefully arranged with a parallel data flow to effectively improve processing speed and reduce the number of memory access. The proposed architecture presents minimum latency, maximum throughput, and full utilization of memory resources. It achieves 48 cycles/macro-block throughput and 56 ycles/macro-block latency for the H.264/AVC decoding.
誌謝..................................................i
摘要..................................................ii
Abstract..............................................ii
圖目錄................................................iv
圖目錄................................................iv
表目錄................................................v
第一章 緒論...........................................1
1.1 前言..............................................1
1.2 H.264 視訊壓縮標準簡介............................2
1.3 研究動機及目的....................................7
1.4 章節組織 .........................................8
第二章 去區塊濾波器原理及演算法介紹...................9
2.1 去區塊濾波器(Deblocking Filter)原理簡介...........9
2.2 區塊邊界強度(Boundary Strength)分析...............11
2.3 濾波器的取樣層級濾波(Sample-Level Filtering)簡介..13
2.4 巨集區塊的濾波順序................................16
2.5 去區塊濾波器演算法運算處理........................17
2.5.1 標準模式濾波運算原理 (Standard Mode Filtering)..17
2.5.2 強力模式濾波運算原理 (Strong Mode Filtering)....19
第三章 相關文獻探討...................................21
第四章 混合式濾波序列的高產能去區塊濾波器硬體實作.....23
4.1 混合式濾波序列的高產能去區塊濾波器之濾波順序......23
4.2 記憶體架構與組織..................................30
4.3 混合式濾波序列的高產能去區塊濾波器之硬體架構......32
第五章 實驗數據分析與硬體化實作方式...................34
第六章 結論...........................................37
參考文獻..............................................38
[1]Joint Video Team of ITU-T and ISO/IEC JTC 1, “Draft ITU-T Recommendation and Final Draft International Standard of Joint Video Specification (ITU-T Rec. H.264 ISO/IEC 14496-10 AVC),” Joint Video Team (JVT) of ISO/IEC MPEG and ITU-T VCEG, JVT-G050, Mar. 2003.
[2]T. Wiegand, G. J. Sullivan, G. Bjontegaard, and A. Luthra, “Overview of the H.264/AVC video coding standard,” IEEE Transactions on Circuits and Systems for Video Technology., vol.13, no. 7, pp. 560-576, Jul. 2003.
[3]P. List, A. Joch, J. Lainema, G. Bjøntegaard, and M. Karczewicz, “Adaptive deblocking filter,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 13, no. 7, pp. 614-619, Jul. 2003.
[4]Bin Sheng, Wen Gao and Di Wu, “An implemented architecture of deblocking filter for H.264/AVC,” Proceedings of IEEE International Conference on Image Processing, vol. 1, pp. 665-668, Oct. 2004.
[5]Yi-Chih Chao, Ji-Kun Lin; Jar-Ferr Yang, Bin-Da Liu, “A high throughput and data reuse architecture for H.264/AVC deblocking filter,” Proceedings of IEEE Asia and South Pacific Conference Circuits Systems, pp. 1260-1263, Dec. 2006.
[6]Shen-Yu Shih, Cheng-Ru Chang, Youn-Long Lin, “A near optimal deblocking filter for H.264 advanced video coding, ” Proceedings of IEEE Asia and South Pacific Design Automation Conference, pp. 170–175, Jan. 2006.
[7]Qing Chen, Wei Zheng, Jian Fang, Kai Luo, Bing Shi, Ming Zhang, Xianmin Zhang, “A pipelined hardware architecture of deblocking filter in H.264/AVC,” Proceedings of Third International Conference Communications and Network in China, pp. 815-819, 2008.
[8]Chung-Ming Chen, Chung-Ho Chen, “Configurable VLSI architecture for deblocking filter in H.264/AVC,” IEEE Transactions on Very Large Scale Integration System, vol. 16, no. 8, pp. 1072–1082, Aug. 2008.
[9]TOBAJAS F., CALLICO G.M., PEREZ P.A., ARMAS V., SARMIENTO R.: “An efficient double-filter hardware architecture for H.264/AVC deblocking filtering,” IEEE Transactions on Consumer Electronics, vol. 54, no. 1, pp. 131–139, Feb. 2008.
[10]Cheng-An Chien, Hsiu-Cheng Chang, and Jiun-In Guo, “A High throughput In-Loop de-blocking filter supporting H.264/AVC BP/MP/HP video coding,” Proceedings of IEEE Asia Pacific Conference on Circuits and Systems, pp. 312-315, Nov. 2008.
[11]Tsung-han Tsai, Yu-nan Pan, “High Efficient H.264/AVC Deblocking Filter Architecture for Real-time QFHD,” IEEE Transactions on Consumer Electronics , vol. 55, no. 4, pp. 2248-2256, Nov. 2009.
[12]Xiaoliang Chen, Weiyi Xia, Xiaofeng Lu, “A High-throughput Low-power Hardware Architecture for H.264 Deblocking Filter,” Proceedings of 2010 2nd International Conference on Computer Engineering and Technology, vol. 2, pp. V2-561-V2-565, 2010.
[13]Yuan-Chun Lin, Youn-Long Lin, “A two-result-per-cycle deblocking filter architecture for QFHD H.264/AVC decoder,” IEEE Transactions on Very Large Scale Integration System, vol. 17, no. 6, pp. 838-843, Jun. 2009.
[14]K.-H. Chen, “48 Cycles-per-macro block deblocking filter accelerator for high-resolution H.264/AVC decoding,” Circuits, Devices & Systems, IET, vol. 4, iss. 3, pp. 196-206, Feb. 2010
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