臺灣博碩士論文加值系統

多晶矽薄膜電晶體很廣泛得被應用在主動式液晶顯示器上。然而，多晶矽薄膜電晶體的漏電流和非晶矽薄膜電晶體相比高出許多，由於汲極端空乏區的強大電場誘使載子經由晶粒邊界的缺陷產生漏電流，造成元件不穩定性，阻礙了多晶矽薄膜電晶體在高效能上的應用。
為了降低汲極端的高電場所導致的漏電流，許多結構陸續被提出來，像是offset-gate TFT、輕摻雜汲極薄膜電晶體(Lightly Doped Drain TFT)，雖然都可以有效的降低汲極端的電場，然而，對於offset-gate 架構來說，在開電流時卻存在著強大的寄生電阻；對於輕摻雜汲極架構而言，離子佈植的濃度較難去調控，且兩次離子佈值的損害，使元件特性退化，後來又有人提出RSD (raised source/drain)結構降低汲極端電場，增加元件的寬度來改善開狀態的電流，使元件尺寸無法縮小，有些RSD製程複雜，需要用到化學機械研磨(chemical machine polish，CMP)。
本研究提出一個“ 新式不對稱汲極端低電場薄膜電晶體 ”，此結構在汲極端增厚，即所謂的抬升汲極端，形成raised drain的架構，並且在靠近汲極端上方處，加上較厚的介電層，有效地降低了汲極端的電場，抑制了漏電流，減少了通道的離子撞擊。而源極端不對稱的設計，使開狀態時的電流能維持一個高電流的特性。除此之外，此結構的製程簡單，我們也經由模擬顯示，此結構維持了開狀態時電流和非常低的電場，不僅增加了元件的穩定性並提高了元件的效能。

Recently, polycrystalline silicon thin film transistors have been widely application inactive matrix liquid crystal displays (AMLCDs). However, the undesired off-state leakage current of poly-Si TFT is much higher than the amorphous-Si TFT. It has been reported that the conduction mechanism for the off-state leakage current is the field emission via grain boundary. The off-state leakage current result in unstable of the device, even block the application in high performance for poly-Si TFTs.
Therefore, to reduce the drain electric field, many methods have been proposed, such as offset gate structure, lightly doped drain structure, they both can reduce the drain electric field. However, the on-state current with high series resistance for the offset gated structure and the difficulty in doping control, implant damage for LDD structure also degrade device performance. Than the RSD structure was proposed to reduce high electric field near the drain and increase device width to improve on-state current, so the device size can’t minify. And some RSD structures need CMP process.
In this research, “A Novel Asymmetric Poly-Si TFT with Low Drain Electric Field” is proposed. In this studying, we use a thick drain and with thick dielectric layer near the drain, reducing the drain electric field effectively, leading to the suppression of the leakage current effect and degrading the impact ionization in the channel. The source of asymmetric design can maintain a high on-state current and the process of the structure is simple. In our simulation result, the new structure maintain the on-state current and has greatly low electric field near the drain, not only increase device stability but also improve device performance.

第一章 緒論 1
1.1 薄膜電晶體簡介與應用 1
1.2 非晶矽薄膜電晶體 2
1.3 複晶矽薄膜電晶體 2
1.4 複晶矽薄膜關鍵製造技術 4
1.4.1 直接沉積複晶矽薄膜 5
1.4.2 非晶矽沉積再回火 5
1.5 薄膜電晶體之不理想效應 9
1.5.1 漏電流效應(Leakage Current Effect) 10
1.5.2 熱載子效應(Hot Carrier Effect) 12
1.5.3 扭結效應(Kink Effect) 14
1.6 薄膜電晶體之常見結構 16
1.7 研究方向與目的 21
1.8 研究架構 22
第二章 文獻回顧與結構設計 23
2.1 歷史文獻回顧 23
2.1.1 Elevated Channel Thin Film Transistor 23
2.1.2 Different Dielectric Thin Film Transistor 24
2.2 新提出之薄膜電晶體之設計 25
第三章 新提出不對稱低電場薄膜電晶體模擬分析 26
3.1 前言 26
3.2 模擬分析 26
3.3 製程參數模擬 32
3.4 問題驗證
3.1.1 錯位 34
3.1.2 過蝕刻 34
第四章 新提出不對稱低電場薄膜電晶體之實作與結果討論 38
4.1 前言 38
4.2 實驗製程步驟 38
4.3 電性參數之萃取 43
4.4 結果與討論 47
4.4.1 Layout設計圖 47
4.4.2 新提出薄膜電晶體之SEM圖 49
4.4.3 新提出薄膜電晶體之轉換曲線 50
4.4.4 新提出薄膜電晶體之輸出曲線 52
4.4.5 新提出薄膜電晶體對偏壓應力效應的影響 53
4.4.6 新提出薄膜電晶體反向偏壓之轉換曲線 56
第五章 結論 57
參考文獻 58

圖目錄
圖1.1 金屬鎳誘發結晶示意圖 8
圖1.2 傳統複晶矽薄膜電晶體 9
圖1.3 三種不理想效應 10
圖1.4漏電流效應 12
圖1.5熱載子效應 13
圖1.6扭結效應 15
圖1.7 kink effect之寄生BJT與Kink current 16
圖1.8 offset結構 17
圖1.9 LDD結構 17
圖1.10 GOLDD結構 18
圖1.11 Air Cavity結構 19
圖1.12 FID結構 19
圖1.13 RSD結構 20
圖2.1 水平電場之測試 24
圖2.2 不同介電層之薄膜電晶體 24
圖2.3 新提出之薄膜電晶體知示意圖 25
圖3.1 傳統與新提出的複晶矽薄膜電晶體的結構圖 27
圖3.2傳統、新提出的薄膜電晶體電場濃度分佈圖和2D電場輸出特性圖 29
圖3.3 2D傳統型與新提出的薄膜電晶體電流特性輸出圖 30
圖3.4傳統型與新提出的複晶矽薄膜電晶體的離子撞擊分佈圖 31
圖3.5新提出薄膜電晶體不同介電材質的結構圖 32
圖3.6 新提出的薄膜電晶體對於不同介電層和不同厚度的2D電流輸出特性圖與電場特性輸出圖 33
圖3.7 2D misaligned電流特性輸出圖 34
圖3.8選擇蝕刻前後的結構圖、2D新提出與過蝕刻的薄膜電晶體電流特性輸出圖與2D新提出與過蝕刻的薄膜電晶體電場特性輸出圖 36
圖4.1 新提出結構薄膜電晶體的關鍵製程步驟圖 43
圖4.2 Layout設計圖 48
圖4.3 Layout俯視 48
圖4.4 元件的SEM剖面圖 49
圖4.5 SEM單邊剖面放大圖 50
圖4.6 新提出之薄膜電晶體與傳統型轉換曲線 51
圖4.7 新提出之薄膜電晶體與傳統之輸出曲線圖 52
圖4.8 傳統型TFT與新提出TFT，在偏壓Vgs=10V , Vds=15V從0s到7000的轉換曲線圖 54
圖4.9 傳統型與新提出之薄膜電晶體，在偏壓Vgs=14V , Vds=10V從0s到4500s的轉換曲線圖 56
圖4.10新提出之薄膜電晶體反向偏壓與傳統型轉換曲線 56

表目錄
表1.1 薄膜電晶體技術分類比較表 4
表1.2 複晶矽製造技術比較 5
表3.1 新提出之薄膜電晶體與傳統電性的比較 37
表4.1 新提出之薄膜電晶體與傳統型之關鍵參數 52

公式
公式3.1 漏電流公式 37
公式4.1 臨界電壓萃取電流公式 44
公式 4.2 次臨界區織T萃取公式 45
公式.4.3 薄膜電晶體之電流公式 46
公式.4.4 轉導係數公式 46
公式.4.5 電子遷移率公式 46

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