臺灣博碩士論文加值系統

隨著科技產業進步的要求與半導體製程的快速發展，以致積體電路偏壓的需求不斷的下降，市場的需求不僅要求體積小、速度快並朝向多功能整合的系統發展，相對的消耗的電流就越多。當電路的佈局越來越緊密與複雜，元件及走線間的距離縮小，造成許多敏感電路受到干擾或走線間的耦合現象，使得電路的效能減低或產生誤動作，為了避免電子產品產生過高的電磁輻射，所以在設計上我們就必須考慮電磁相容(Electromagnetic Compatibility)的問題。
本論文首先介紹電源完整性的理論基礎，經由一些設計準則來設計與模擬電源完整性對電磁干擾的問題，探討類比與數位電路在不同的接地措施所產生的干擾，再使用標準IEC 61967-5 工作台法拉第箱體(Workbench Faraday Cage method)量測法，量測分析共地與割地所產生的共模輻射雜訊並且與三米全電波暗室所量測的遠場輻射位準做比較。

With the requirements of the progress of the technology industry and the rapid development of the semiconductor manufacturing process, resulting in integrated circuit bias incessantly decline in demand. Market demand requires not only small size, speed and work towards to the development of multi-function integrated system, relative consumption of the more current. As the closely and complex layout of the circuit, and shorten the distance between components and traces, making sensitive circuit affected by the interference or the coupling between the traces, and degrade the performance of the circuit, even cause errors. In order to avoid electronic products generate excessive electromagnetic radiation, the problem of EMC should be taken account when designing the Integrated Circuit.
This thesis first describes the theoretical basis of the power integrity, with some design criteria to design and simulation for power integrity problems of electromagnetic interference, to investigate the interference of the analog and digital circuits on different ground measures, and then use the standard IEC 61967-5 Workbench Faraday Cage method, measurement analysis common-mode radiation noise from common and Separate ground, and comparing with far-field measurements of radiation levels from three meters fully anechoic chamber.

致 謝 i
摘 要 ii
Abstract iii
目 錄 iv
圖目錄 vi
表目錄 xii
第一章、緒論 1
1.1 前言 1
1.2 研究動機 1
1.3 論文大綱 3
第二章、電源完整性的介紹 4
2.1 同步切換雜訊[1] 4
2.2 電源平面的目標阻抗[2] 7
2.3 印刷電路板電源與接地平面共振效應 11
2.4 去耦合電容之作用與特性[5] 12
2.5 差模輻射效應[6] 15
2.6 共模輻射效應[6] 16
第三章、印刷電路板之電源完整性設計準則與模擬分析 18
3.1 電源完整性設計準則簡介 18
3.2 電路板設計與模擬 21
3.3 電源佈局設計對雜訊的影響[10] 22
3.4 去耦合電容之選用與位置的影響[11] 28
第四章、類比與數位電路接地措施的效應分析 41
4.1 類比與數位電路板的設計[13] 41
4.2 數位電路之切換雜訊對類比電路增益的影響[14] 48
4.2.1 割地電路測試板 48
4.2.2 共地電路測試板 50
4.3 使用工作台法拉第箱體量測電磁干擾效應[15] 54
4.3.1 工作台法拉第箱體量測原理 54
4.3.2 工作台法拉第箱體量測配置 56
4.3.3 積體電路電磁干擾效應量測 59
4.4 工作台法拉第箱體量測之位準與遠場輻射位準分析 66
第五章、結論 80
參考文獻 82

[1]Madhavan Swaminathan and A. Ege Engin, “Power Integrity Modeling and Design for Semiconductors and Systems” Chapter 1.2, Prentice Hall, 2008.
[2]Madhavan Swaminathan and A. Ege Engin, “Power Integrity Modeling and Design for Semiconductors and Systems” Chapter 1.3, Prentice Hall, 2008.
[3]David M. Pozar, “Microwave Engineering”, 3rd Edition, Chapter 4, John Wiley & Sons, 2005.
[4]Mikhhail Popovich, Andrey V. Mezhiba, Eby G. Friedman “Power Distribution Networks with On-Chip Decoupling Capacitors” Chapter 5, Springer.
[5]Mark Alexander, “Power Distribution System (PDS) Design: Using Bypass/Decoupling Capacitors” Xilinx, April 5, 2004
[6]Henry W. Ott, “Electromagnetic Compatibility Engineering”, Chapter 12, Wiley , 2009.
[7]Mark I. Montrose, “PCB Design Techniques for EMC Compliance” Chapter 2
[8]John Andresakis, “Measuring Performance of Embedded Capacitance Layers”.
[9]Henry W. Ott, “Electromagnetic Compatibility Engineering”, Chapter 11, Wiley , 2009.
[10]柯昆助, ” 印刷電路板上電源導線佈線和電容佈置對電磁干擾之影響與分析”
[11]James L. Knighten, Bruce Archambeault, Jun Fan, Giuseppe Selli, Liang Xue, Samuel Connor, James L. Drewniak, “Ceramic SMT Decoupling Capacitors – Does Location Matter ?” IEEE, 2006
[12]http://www.murata.com
[13]何滿龍，孔繁喜，林坤熒，“ 射頻電路設計實習“，育英科技有限公司，增訂版，2003年11月，第四章。
[14]Rob Reeder, “Considerations on High-Speed Converter PCB Design, Part 1: Power and Ground Planes”.
[15]IEC 61967-5,Integrated circuits - Measurement of electromagnetic emissions, 150 kHz to 1 GHz - Part 5: Measurement of conducted emissions - Workbench Faraday Cage method.
[16]Madhavan Swaminathan and A. Ege Engin, “Power Integrity Modeling and Design for Semiconductors and Systems” Chapter 5, Prentice Hall, 2008.