跳到主要內容

臺灣博碩士論文加值系統

(44.212.99.248) 您好!臺灣時間:2023/01/28 11:33
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果 :::

詳目顯示

我願授權國圖
: 
twitterline
研究生:許志謙
論文名稱:使用高介電係數絕緣層之金氧半場效電晶體中界面熱穩定性之研究
論文名稱(外文):Thermal Stability Analysis of Interfacial Layer in MOSFETs with High-K Dielectric
指導教授:陳啟文陳啟文引用關係
學位類別:碩士
校院名稱:明新科技大學
系所名稱:電子工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2011
畢業學年度:100
語文別:中文
論文頁數:74
中文關鍵詞:摩爾定理高介電係數界面層應變矽絕緣膜上形成單結晶矽基板電荷汲引技術
外文關鍵詞:Moore lawHigh-k dielectricinterfacial layerStrained siliconSOI(Silicon-on-Insulator)Charge Pumping
相關次數:
  • 被引用被引用:0
  • 點閱點閱:121
  • 評分評分:
  • 下載下載:0
  • 收藏至我的研究室書目清單書目收藏:0
隨著製程技術不斷的改變下,元件尺寸不斷的微縮,根據摩爾定理的預言,在固定面積矽晶圓上的電晶體數目,每十八個月會增加一倍。這項定律至今完全正確,不過由於製造過程中的電晶體密度增加,因此相關的製程開發成本也隨之大幅提升。為了能夠繼續遵循摩爾定律的演進,產業界就從所能開發出材料的方向下去進行,這當然包括高介電係數界面層、應變矽、及絕緣膜上形成單結晶矽基板的半導體等。這才是半導體產業遵循摩爾定理的新方向,製程的微縮再也不是延續摩爾定理的坦途。
本文就高介電係數閘極電晶體在不同的高介電係數材料、不同界面層製程方式以及不同的界面層結構的條件下比較元件的基本特性,並且透過升溫及電荷汲引技術研究電荷捕捉/散逸效應,對界面缺陷密度的大小及分布以及受到溫度的改變產生的效應。進而了解到閘極氧化層之元件特性與界面品質。實驗發現使用高介電係數材料HfSiON,製程方式使用N2O plasma,以及界面層材料使用SiO2具有較佳的電性,另外發現元件在室溫下量測與加熱後靜置至室溫的量測出的電性是相近的。

With the process technology is constantly changing, the device dimensions continue to microfilm, on a fixed area of the silicon wafer according to the Moore law, the number of transistors every 18 months will increase to double. The law of so far is completely correct, but due to the increase in the density of transistors in the manufacturing process, process development costs also will be significantly improved. Order to be able to continue to follow the evolution of Moore's Law, the industry from the best to develop the the direction of the material to down, which of course includes a high dielectric constant interfacial layer, strained silicon, and SOI(Silicon-on-Insulator). This is the new direction of the semiconductor industry to follow Moore's law, the microfilm process is no longer the continuation of Moore Theorem smooth sailing.
In this paper, the coefficient of gate of High-k dielectric polar electric crystal in different High-k materials, different interface layer system Cheng way and a different interface layer structure of the comparison element of the basic features, and through warming and Charge Pumping technology research charge capture / dissipation effect, the effect on the size of the interface defect density and distribution, as well as by temperature change. And then learned that the gate oxide layer of the device characteristics and interface quality. The experiment found that the use of high dielectric constant material throughput also make HfSiON, a process using N2O plasma, and the interface layer material SiO2 has a better electrical, the other components standing in the room temperature measured under heating to room temperature measurements the electrical properties are similar.

摘要 2
Abstract 3
致謝 4
目錄 5
表目錄 7
圖目錄 8
第一章 緒論 11
1.1 金氧半場效電晶體(MOSFET) 11
1.2 金氧半二極體 12
1.2.1 功函數差 12
1.2.2 界面缺陷與氧化層電荷 13
1.3高界電閘極氧化層(High-K Gate Dielectric) 15
1.3.1 不理想效應 16
1.3.2 高介電材料選用 17
1.4 界面層(Interfacial layer) 18
1.5 界面層製程 19
1.5.1氧化 19
1.5.2快速熱氧化(RTO) 20
1.6 電荷汲引技術量測方法 20
1.6.1 實驗原理 21
1.7 可靠度(Reliability) 22
1.7.1 熱載子射入(HCI) 23
1.8 論文架構 25
第二章 High-k元件製作與實驗方法 26
2.1 不同界面層材料之High-k CMOSFETs 製作方法 26
2.2 不同界面層製程對HfSiON-CMOSFETs 電性實驗 27
2.3 不同界面層製程對HfO2-CMOSFETs 電性實驗 28
2.4 實驗量測方法 29
2.4.1 ID-VGS特性曲線萃取 29
2.4.1.1 次臨界特性 30
2.4.1.2 臨界電壓之調整(VT adjustment) 33
2.4.1.3 閘極衍生汲極漏電流量測( Gate-Induced-Drain-Leakage Current Measurement, GIDL) 35
2.4.2 ID -VDS特性曲線 35
2.4.3 IG-VGS特性曲線 39
2.4.4Charge pumping 39
2.5 晶圓探測 40
2.6 實驗量測流程及參數設定 41
第三章實驗結果與討論 42
3.1不同界面層材料之High-k CMOSFETs 製作方法 42
3.2不同界面層製程對HfSiON-CMOSFETs 電性實驗 51
3.3不同界面層製程對HfO2-CMOSFETs 電性實驗 60
3.4元件熱穩定性之研究 69
第四章結論 77
參考文獻 81
作者簡介 83

[1] S. M. Sze, “Semiconductor Devices, Physics and Technology”, 2nd Ed, 2003.
[2] Q. Q. Lo, D. L. Kwong, “Reliability characteristics of metal-oxide -semiconductor capacitors with chemical vapor deposited Ta2O5 gate dielectrics,” in Appl. Phys. Lett.62, p.975, 1993.
[3] Ma ,T. P. (1998). Electron Devices. IEEE Trans,vol. 45, 680.
[4] The International Technology Roadmap for Semiconductors, 2009 ed., Semiconductor Industry Assoc.
[5] H. W. Chen.”Comparison of relevant properties for different high-k materials”(2009)
[6] H. Wong, H. Iwai, “On the Scaling issues and high-κ replacement of ultrathin gate dielectrics for
nanoscale MOS transistors,” ELSEVIER Microelectronic Engineering, Vol. 83, Issue. 10, pp.
1867-1904, 2006.
[7] H. Itokawa et al., Ext. abs. Solid Sate Device and Material (SSDM). Pp.158-159(1999).
[8] Z. Luo et al., Paper P 2.1 in the 30th IEEE Semiconductor Interface Specialists Conference (SISC)
(Dec. 1999)
[9] Wenjuan Zhu Jin-Ping Han Ma, T.P. Dept. of Electr. Eng., Yale Univ.,“Mobility measurement and
degradation mechanisms of MOSFETs made with ultrathin high-k dielectrics ",Electron Devices,
IEEE Transactions ,Jan. 2004.
[10] G. Lucovsky, Y. Zhang, G. B. Rayner, Jr., G. Appel, and H. Ade J. L. Whitten,“Electronic structure
of high-k transition metal oxides and their silicate and aluminatealloys", Journal of Vacuum Science
&; Technology B: Microelectronics and Nanometer Structures -- July 2002 -- Volume 20, Issue 4, pp.
1739-1747
[11] CR Parthasarathy, M. Denais, V. Huard, G. Ribes, E. Vincent, A. Bravaix, “Characterization and
Modeling NBTI For Design-In Reliability,” IEEE International Integrated Reliability Workshop
Final Report, pp. 158-162, 2005.
[12] Leroux, C. Mitard, J. Ghibaudo, G. Garros, X. Reimbold, G. Guillaumor, B. Martin, F. ,
“Characterization and modeling of hysteresis phenomena in high K dielectrics" ,Electron Devices
Meeting, 2004.IEDM Technical Digest. IEEE International,13-15 Dec. 2004
[13] 劉傳璽、陳進來.” Semiconductor Device Physics and Process: Theory &; Practice”, 2nd Ed, 2006.
[14] Hong Xiao, ”Introduction to Semiconductor manufacturing Technology ” 3rd ed,2005.
[15] J. S. Bruglar and P. G. A. Jaspers, “Charge pumping in MOS Devices,” IEEE Transactions on
Electron Devices, Vol.16, 1969, 9.297.
[16] 傅寬裕.”Reliability in Semiconductor IC Products”(2009)
[17] K. Shiraishi, K. Yamada, K. Torii, Y.Akasaka, K. Nakajima, M. Kohno, T. Chikyo, H. Kitajima, and
T. Arikado, “Physics in Fermi Level Pinning at the Poly Si/Hf-based High-K Oxide Interface,” IEEE
Symposium on VLSI Technology Digest of Technical Papers, pp.108-109 ,2004.
[18]T. hayashi, Y.Nishida, S.Sakashita, M. Mizutani, S. Yamanari, M. Higashi, T.Kawahara, M. Inoue, J.
Yugami, J. Tsuchimoto, K. Shiga, N. Murata, H. Sayama, T. Yamashita, H. Oda, T. Kuroi, T. Eimori,
and Y. Inoue, “Cost Worthy and High Perfrmance LSTP CMIS; Poly-Si/HfSiON nMIS and
Poly-Si/TiN/HfSiON pMIS,” IEEE International Electron Devices Meeting, pp. 1-4, 2006.
[19]Dr. Wen-Kuan Yeh, Dr. Chao-Hsin Chien, Shau-Hua Syu, “The Investigations of Negative Bias
Temperature Instability on P-MOSFETs with High-k Dielectrics in 90nm Technology. pp. 1, pp. 9-11,
pp. 48-50., 2006.

連結至畢業學校之論文網頁點我開啟連結
註: 此連結為研究生畢業學校所提供,不一定有電子全文可供下載,若連結有誤,請點選上方之〝勘誤回報〞功能,我們會盡快修正,謝謝!
QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top