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研究生:朱明茂
研究生(外文):Ming-MaoChu
論文名稱:應用於22 奈米級(含以下)邏輯互補金屬氧化物半導體中段製程整合研究
論文名稱(外文):Scaling of the MOL Fabrication Process Integration for Logic CMOS to 22 nm Node and Beyond
指導教授:周榮華周榮華引用關係
指導教授(外文):Jung-Hua Chou
學位類別:博士
校院名稱:國立成功大學
系所名稱:工程科學系碩博士班
學門:工程學門
學類:綜合工程學類
論文種類:學術論文
論文出版年:2012
畢業學年度:100
語文別:英文
論文頁數:229
中文關鍵詞:中段製程金屬矽化物蕭特基障壁準位寄生電阻製程變異量
外文關鍵詞:MOL processSilicideSchottky barrier heightParasitic resistivityProcess induced variation
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互補金屬氧化物半導體 (CMOS) 微縮到50 奈米以下閘極線寬後,所有的元件都縮擠到非常小的空間,小到幾乎抵觸到物理的極限,這為製程技術帶來了極大的挑戰。製程微縮技術的發展是持續推動改善金屬互補氧化物半導體的三個基本功能;他們分別是靜電力(用來控制閘極電流開與關),閘通道載子移動率(用於高速切換),與寄生電阻(用來調變驅動電流及電導特性)。當前兩項不變時,降低寄生電阻可以降低電功率消耗或是令電晶體積體電路進行更高速運算。互補金屬氧化物半導體微縮到32 奈米以下節點時,電晶體外部阻抗值將超越閘極通道阻抗值。已知金屬矽化物接點阻抗佔n型金屬互補氧化物半導體總電阻的16.7 %,而降低金屬矽化物與矽介面的蕭特基障壁準位(SBH)可以有效降低寄生電阻。因此,以調整蕭特基障壁準位為導向的中段製程(MOL)技術來改善整體寄生電阻,就成為互補金屬氧化物半導體積體電路進一步微縮的可行途徑。
接點金屬矽化物主要的製造方法可以細分成六個製程模組;分別是:矽化製程前對n型與p型金屬互補氧化物半導體的離子佈植, 矽化製程前晶圓表面清理,金屬薄膜沉積,第一道熱處理加工,選擇性蝕刻, 及第二道熱處理加工。維持金屬矽化物的熱穩定性與調降蕭特基障壁準位同等重要,且兩者都可以透過在矽化物、介面層或在矽材上植入摻雜來達成;其中所需要的個別加工技術,則是可以透過目前鎳化矽(NiSi)製程架構的重組來整合。
在製程技術整合的可行性分析中,探討七種可行的製程架構方案,可以分別或同時運用矽基材改造工法、金屬選別、摻雜堆積工法與雙金屬矽化物工法來達成不同程度的蕭特基障壁準位調降結果。然而,採用愈多的工法也會增加製程的複雜度。目前用於 32奈米節點的傳統整合架構有14道製程工序,在這個架構下,矽基材改造工法、摻雜堆積工法與金屬摻雜都可以納入製程整合。如果要加上雙金屬矽化物工法,則依照選用的金屬材料所需的熱處理特性,製程工序會增加到分別為 16、 17、 19、 20 道。如果要加上矽化製程後離子植入(IAS)工法,那製程工序會分別增加到23及29道。
在生產線上,加工機具的精度與量測儀器的解析度限制了製程偏移量的控制能力。在最糟狀況模擬當中,上述七個方案的累積製程誤差會導致金屬矽化物接點阻抗分別有4.18% 乃至7.68% 的變異幅度。這項阻抗變異量也會等比例地衝擊半導體元件電流-電壓響應特性。在這七個製程整合方案中,有三個方案可以把總變異幅度控制在5% 以內。用最佳的調降蕭特基障壁準位(SBH)工法,試整合入三個可以將總變異幅度控制在5% 以內的製程方案,可以得到一組優化後的製程架構。 這個優化的製程架構同時採用雙矽化物工法(NiPt-nMOS, Pt-pMOS)與離子堆積工法 (硫 (Sulfur)或硒(Selenium));這項製程整合架構可以降低n型互補金屬氧化物半導體的接點金屬矽化物電阻達20倍,降低p型互補金屬氧化物半導體接點金屬矽化物電阻達6.16倍,元件電流-電壓響應性能的總變異量則是控制在 4.98 % 水準。也同時降低n型互補金屬氧化物半導體總電阻達3.34倍,降低p型互補金屬氧化物半導體總電阻0.28 %,選用的金屬矽化物材料熱穩定性則是維持在與目前32奈米節點相同的 750-800℃範圍。 這個製程整合架構可以運用在 22 奈米技術節點的半導體元件製造, 也可以延用到22奈米以下至少一個技術節點。

CMOS scaling to sub-50 nm of physical gate width is pulling all the device components into a smaller geometry that bumps to the limit of physics and poses a tremendous challenge to the fabrication process technology. The desired process innovation is pushing three basic functions of CMOS transistors in parallel; namely, electrostatic force that holds the ON/OFF state, channel mobility for higher switching frequencies, and parasitic resistance that modulates both effective driving current and transconductance. When the first two items are fixed, lowering the parasitic resistivity leads to either lower power consumption or a higher switching frequency of CMOS ICs.
After the 32 nm node, the CMOS external resistivity becomes larger than channel resistivity of the gate. The contact silicide contributes 16.7 % of total resistance to nMOS and the process techniques of adjusting SBH on silicide/silicon interface can reduce it effectively. The SBH modulation oriented mid-of-line (MOL) fabrication to reduce the overall parasitic resistance becomes a desirable path for further CMOS scaling.
The main fabrication processes of silicide can be modularized to six sub-modules; namely, pre-silicide doping for n-/pMOS, pre-silicide clean, metal film deposition, 1st rapid thermal process, selective etch, and 2nd rapid thermal process. The thermal stability and SBH modulation are equally important and both can be achieved by impurity additive in different locations of the silicide, interface and silicon. The required individual process techniques are found to be integratable by reorganizing current NiSi silicide base process schemes.
In the feasibility simulation of integrated scenarios which include substrate modification techniques, metals selection, dopant segregation techniques and dual silicide techniques, it is observed that seven possible process integration scenarios can incorporate various techniques and modulate SBH to various extents. However, scenarios which include more techniques also lead to higher process complexity. A typical integration scheme which serves the 32 nm node has a total of 14 process steps. In this situation, the wafer substrate processing, dopant segregation and metal impurity techniques can be integrated. If the dual silicide technique is added, depending on the thermal annealing program of the selected metals, the total process steps will grow to 16, 17, 19 or 20 steps. If the implant after silicide (IAS) technique is incorporated, the process will grow to 23 or 29 steps.
In the fabrication environment, both tool precision and metrology resolution limit the process capability on the controllable deviation. Depending on the process integration scheme used, in the worst case simulation for all the cases explored, the accumulated process variation can lead to total silicide resistivity deviation from 4.18 % to 7.68 %. This resistivity deviation also impacts the CMOS device current-voltage (I-V) response proportionally. Within these cases of process integration schemes, three of them show the capability of controlling the deviation within 5 %. By incorporating the best case of the SBH modulation techniques into the process scheme that has 〈 5% total variation, the optimal integration scheme is determined. This optimal process integration employs dual silicide techniques (NiPt for nMOS, Pt for pMOS) and dopant segregation techniques (sulfur (S) or selenium (Se)) to improve the contact silicide parasitic resistivity with a factor of 20 on nMOS and 6.16 on pMOS. It leads to a total CMOS resistivity reduction by a factor of 3.34 on nMOS and 0.28 % on pMOS; meanwhile, controlling the device I-V deviation on the 4.98 % level. The selected silicide material maintains the same level of 750-800 ℃ thermal stability as that of the 32 nm node. This optimal process integration scheme is applicable to the 22 nm node and extendable at least one more node beyond the 22 nm node.

Table of Contents

Chapter 1: Introduction ………………………………………………………..……..…. 1
1.1 Motivation of this work ……………………………………………………..……… 1
1.2 Conventional MOSFETs scaling and potential limits …………………… 7
1.3 Next generation parasitic resistance scaling ……………………………… 21
1.4 Process challenge for contact silicide (RCSD) scaling …………..… 27
1.5 Thesis organization ……………………………………………………….……..… 36
Chapter 2: Schottky barrier height oriented fabrication process integration ……… 37
2.1 Schottky barrier theories for semiconductor …………………………………….... 37
2.2 Review on contact resistivity engineering for Metal-Semiconductor ……………44
2.2.1 NiSi phase and thermal stability …………………………….………..……. 49
2.2.2 Innovation on silicon substrate preparation for NiSi thermal stability ….… 57
2.2.3 Silicide work function tuning ………………………………….……….…. 58
2.2.4 Passivation of silicide grain boundary and silicide-silicon Interface ……... 62
2.2.5 Silicide to silicon interface band edge engineering………………………… 64
2.2.6 Summary of SBH modulation techniques……………….…………..……... 73
2.3 Ideal Ni(X)Si and Ni(X)Si-Si interface material engineering for SBH modulation..74
2.3.1 The ideal NiSi-Si material engineering that desired………………....…...... 77
2.3.2 Reorganizing MOL fabrication process integration flow …………….….… 80
Chapter 3: Process innovation and metrology control toward 1x nm thickness…..... 84
3.1 Fabrication process innovation, potential limit and error model ………………… 84
3.1.1 Patterning process ……………………………….……………………….. 86
3.1.2 Ion implantation and activation …………………………………………93
3.1.3 Surface preparation before metal thin film deposition …..……....……….... 100
3.1.4 Metal thin film deposition ……………………………….………... 105
3.1.5 Rapid thermal process ……………………………………………...……… 111
3.1.6 Selective etching process …………………………………………………. 123
3.2 Assessment on process modularization and integration …133
3.2.1 Modularization feasibility and process integration scenario simulation…… 133
3.2.2 Metrology allocation for key parameters control ………………………..… 137
3.2.3 Error propagation modeling and process variation controllability ….…..…. 143
3.2.4 Methodology of adaptive modeling, analysis for process control ….….…... 145
3.3 Summary of process integration for new techniques …………149
3.3.1 Overview of process technology innovation and integration………….....… 149
3.3.2 Overview of process error propagation and impact to resistivity ………..... 150
3.3.3 Overview of Process variation models ……………………….….150

Chapter 4: Modeling and simulation for optimal process integration ………152
4.1 Process error modeling and error propagation analysis ………………… 152
4.1.1 Unit process module error modeling …………….. 152
4.1.2 Error propagation and implication to contact silicide resistivity ……… 159
4.2 Optimal integrated processes for SBH modulated device performance ….…166
4.2.1 Worse case simulation for error propagation …………… 166
4.2.2 Best case simulation by SBH modulation ………………….… 173
4.2.3 Optimal integration process in MOL fabrication and scalability ………175
Chapter 5: Conclusions and future perspective …………………… 178
5.1 Conclusions ……………………….……………………… 178
5.2 Future perspectives……………………………………………………………181
REFERENCE ……..……………………………….………………………………….. 184
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