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研究生:劉家榮
研究生(外文):Chia-JungLiu
論文名稱:釕或鉭金屬作為高介電常數介電層之閘極電極特性研究
論文名稱(外文):Characterization of Ru or Ta metal gate electrodes on high-k dielectrics
指導教授:陳貞夙陳貞夙引用關係
指導教授(外文):Jen-Sue Chen
學位類別:碩士
校院名稱:國立成功大學
系所名稱:材料科學及工程學系碩博士班
學門:工程學門
學類:材料工程學類
論文種類:學術論文
論文出版年:2012
畢業學年度:100
語文別:中文
論文頁數:115
中文關鍵詞:高介電常數介電層氧化鉿氧化鈦等效氧化層厚度釕金屬電極鉭金屬電極
外文關鍵詞:High-k dielectricHafnium oxideTitanium oxideEquivalent oxide thickness(EOT)Ruthenium metal gateTantalum metal gate
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本研究使用氧化鉿(HfOx)或氧化鈦/氧化鉿(TiOx/HfOx)作為介電層材料,搭配釕(Ru)或鉭(Ta)做為金屬閘極電極製備成MOS電容元件。以電性量測與材料分析研究不同疊層在初鍍時與熱處理後其電性行為與材料特性。
在矽基材上以磁控濺鍍法製備2 nm HfOx或1 nm TiOx/1 nm HfOx介電薄膜,接著在介電層上濺鍍釕或鉭金屬薄膜製備成MOS電容元件,部分MOS電容元件在氮氣氛中進行400℃退火熱處理10分鐘。為了瞭解其電性行為,以4294A精密阻抗分析儀量測元件的電容-電壓曲線(量測頻率100 kHz),同時以4156C半導體參數分析儀量測元件的電流密度-電壓曲線。為了分析其材料特性,使用高解析穿透式電子顯微鏡(HRTEM)觀察橫截面影像,以了解界面微結構與薄膜實際物理厚度;使用X光光電子能譜儀(XPS)探討各疊層的化學鍵結與縱深分析。
電容-電壓曲線顯示,使用釕金屬電極並搭配HfOx或TiOx/HfOx介電薄膜,在初鍍時的等效氧化層厚度(Equivalent oxide thickness,EOT)分別為2.69 nm與1.53 nm,經過熱處理後的EOT分別為3.68 nm與2.52 nm。使用鉭金屬電極並搭配HfOx或TiOx/HfOx介電薄膜,初鍍時皆顯示非標準的電容-電壓曲線,然而經過熱處理後均展現MOS特性,其EOT分別為1.64 nm與0.87 nm。
電流密度-電壓曲線顯示,使用釕金屬電極並搭配HfOx或TiOx/HfOx介電薄膜,在初鍍時, MOS電容元件於+1V偏壓下的電流密度分別為4.36×10-3 A/cm2與8.09×10-3 A/cm2;經過熱處理後的電流密度均些微降低至2.03×10-3 A/cm2與2.44×10-3 A/cm2。使用鉭金屬電極並搭配HfOx或TiOx/HfOx介電薄膜,在初鍍時, MOS電容元件於+1V偏壓下的電流密度分別高達0.25 A/cm2與0.39 A/cm2,然而經過熱處理後的電流密度均大幅降低至2.76×10-3 A/cm2與4.47×10-3 A/cm2。
由於使用TiOx/HfOx介電薄膜具有較低的等效氧化層厚度(EOT),因此本研究針對釕或鉭金屬電極搭配TiOx/HfOx介電薄膜之疊層進行HRTEM與XPS縱深
材料分析,以探討濺鍍釕或鉭金屬電極時MOS元件材料特性的不同。
HRTEM橫截面影像中顯示所濺鍍TiOx/HfOx介電層為非晶質結構,同時可以得到HfOx與TiOx介電薄膜的實際物理厚度,及存在於介電層/矽基板界面的中介層SiOx厚度。藉由薄膜實際物理厚度、等效氧化層厚度(EOT)與中介層厚度,可以求得介電層的介電常數。初鍍與熱處理後的Ru/TiOx/HfOx/Si MOS電容元件,其介電層的介電常數分別為10.68與8.23;初鍍的Ta/TiOx/HfOx/Si MOS電容元件因不具備標準的電容-電壓曲線,其介電層的介電常數無法計算,然而經過熱處理後顯示其介電常數為59.64。
XPS分析中,若不覆蓋電極,TiOx/HfOx介電薄膜呈現Hf 4+、Ti 4+氧化態。濺鍍約5 nm金屬電極在介電層上,其XPS縱深分析顯示釕金屬電極與TiOx/HfOx介電疊層在初鍍時Ti 2p訊號由Ti 4+所貢獻,顯示TiOx中之Ti以四價氧化態存在。然而使用鉭金屬電極與TiOx/HfOx介電疊層在初鍍時Ti 2p訊號由Ti 4+、Ti 3+、Ti 2+與Ti 0所共同貢獻,顯示TiOx中之Ti呈現多價數氧化態。然而,無論覆蓋釕金屬或鉭金屬電極之MOS結構中,初鍍與熱處理後介電層的XPS能譜皆沒有明顯的改變。
本實驗藉由HRTEM橫截面影像與XPS縱深分析,顯示濺鍍鉭金屬於介電層上時會對其造成影響,導致電性量測時出現非標準的電容-電壓曲線、高漏電流密度。然而,鉭金屬電極搭配TiOx/HfOx經過熱處理後具有低等效氧化層厚度0.87 nm,符合未來高效能CMOS製程中的需求。

In this study, metal-oxide-semiconductor capacitor (MOSCAP) devices were fabricated with hafnium oxide (HfOx) or titanium oxide/hafnium oxide (TiOx/HfOx) as dielectric layer, matching with Ru or Ta as metal gate electrode. Electrical properties and material characteristics of MOSCAP with different gate stacks were investigated when as-deposited and after thermal treatment.
2 nm HfOx or 1nm TiOx / 1nm HfOx dielectric layer were deposited on silicon substrate by sputtering , with Ru or Ta metal thin film on top of dielectric layer as the gate electrode for MOSCAP devices preparation. Some devices were annealed in N2 ambient for 10 minutes at 400℃. Capacitance-voltage (C-V) measurement at 100 kHz and Current density-voltage (J-V) measurement were done by 4294A precision impedence analyzer and 4156C semiconductor parameter analyzer for the understanding of electrical property. High resolution transmission electron microscopy (HRTEM) cross-sectional image is applied to observe the interface structure and the physical thickness of each thin film. X-ray photoelectron spectroscopy (XPS) spectra and depth profiling were done to study the chemical binding and in-depth analysis of the different stacks.
C-V measurement shows that Ru/HfOx/Si and Ru/TiOx/HfOx/Si stacks exhibit equivalent oxide thickness (EOT) of 2.69 nm and 1.53 nm, respectively, when as-deposited, while EOT become 3.68 nm and 2.52 nm, respectively, after annealing. Ta/HfOx/Si and Ta/TiOx/HfOx/Si stacks show abnormal C-V curves when as-deposited, while both exhibit MOS characteristics with EOT 1.64 nm and 0.87 nm after annealing.
J-V measurement shows that Ru/HfOx/Si and Ru/TiOx/HfOx/Si stacks exhibit current density of 4.36×10-3 A/cm2 and 8.09×10-3 A/cm2 at +1V, respectively, when as-deposited, while slightly decrease to 2.03×10-3 A/cm2 and 2.44×10-3 A/cm2 , respectively, after annealing. Ta/HfOx/Si and Ta/TiOx/HfOx/Si stacks exhibit current density of 0.25 A/cm2 and 0.39 A/cm2 at +1V, respectively, when as-deposited, while decrease to 2.76×10-3 A/cm2 and 4.47×10-3 A/cm2, respectively, after annealing.
Lower equivalent oxide thickness is obtained with TiOx/HfOx dielectric; therefore, Ru/TiOx/HfOx/Si and Ta/TiOx/HfOx/Si stacks were prepared for HRTEM image and XPS depth profiling analyses in this experiment to understand the difference in material characteristics with Ru or Ta as gate electrode.
Amorphous structure of the TiOx/HfOx dielectric is seen in HRTEM cross-sectional image and the physical thickness of TiOx, HfOx and SiOx which exists at dielectric/substrate interface is obtained. Dielectric constant of the dielectric layer is extracted with the physical thickness of each layer as mentioned above. As-deposited and annealed Ru/TiOx/HfOx/Si stacks show the dielectric constant of 10.68 and 8.23, respectively. As-deposited Ta/TiOx/HfOx/Si stack is incapable of the extraction, while annealed Ta/TiOx/HfOx/Si stack shows the dielectric constant of 59.64 .
XPS spectra of the sample without capping top electrode show Hf 4+ and Ti 4+ oxidation states in TiOx/HfOx dielectric stack. With sputtering 5 nm Ru metal on top of the dielectric, XPS depth profiling shows Ti 2p is contributed by Ti 4+ in as-deposited Ru/TiOx/HfOx/Si, which demonstrates the presence of tetravalent oxidation state titanium in TiOx. However, in the 5 nm Ta-gate stack, XPS depth profiling shows Ti 2p is contributed together by Ti 4+ , Ti 3+, Ti 2+ and Ti 0 in as-deposited Ta/TiOx/HfOx/Si, which demonstrates the presence of multi-valent oxidation state titanium in TiOx. Nevertheless, XPS spectra show no obvious shifting of binding energy of Ti and Hf core-level electrons in the as-deposited and annealed MOS stacks, no matter capping Ru or Ta as metal gate electrode.
In this study, HRTEM cross-sectional image and XPS depth profiling demonstrate the dielectric has been changed after sputtering Ta metal gate on top, resulting in abnormal C-V curve and high leakage current density in electrical measurement. However, Ta/TiOx/HfOx/Si stack after heat treatment exhibits low equivalent oxide thickness 0.87 nm, showing the feasibility for high performance application in future CMOS technology.

第一章 序論 1
1-1 研究背景 1
1-2 研究目的 5
第二章 理論基礎 7
2-1 金-氧-半場效電晶體(MOSFET) 7
2-2 高介電常數介電層與金屬閘極電極 9
2-3高介電常數材料 13
2-3.1高介電常數材料的需求 13
2-3.2高介電常數材料的發展 19
2-3.3氧化鉿、氧化鈦與氧化鉭之材料基本性質 22
2-3.4氧化鉿、氧化鈦與氧化鉭作為閘極介電層材料之相關文獻探討 26
2-4 金屬閘極電極 30
2-4.1金屬閘極電極的需求 30
2-4.2金屬閘極電極的發展 32
2-4.3釕、鉭之材料基本性質 36
2-4.4釕、鉭作為閘極電極之相關文獻探討 38
第三章 實驗方法與步驟 41
3-1 實驗材料 41
3-1.1 基材(substrates) 41
3-1.2 濺鍍靶材(target) 41
3-1.3 濺鍍及熱處理使用氣氛 41
3-1.4 實驗相關藥品與耗材 42
3-2 實驗設備 43
3-2.1 濺鍍系統 (Sputtering system) 43
3-2.2退火熱處理系統 (Thermal annealing system) 45
3-3實驗流程 46
3-3.1基材清洗(Substrate cleaning) 46
3-3.2 薄膜製備(Thin film sputtering) 46
3-3.3退火熱處理 49
3-3.4 MOS電容器製備 49
3-4 分析儀器 51
3-4.1四點探針儀 (Four-point probe) 51
3-4.2表面粗度儀 (Alpha-step profilometry) 52
3-4.3 X光光電子能譜儀 (XPS) 53
3-4.4穿透式電子顯微鏡 (TEM) 55
3-4.5 精密阻抗分析儀 (Precision impedance analyzer) 56
3-4.6半導體參數分析儀 (semiconductor parameter analyzer) 58
第四章 實驗結果與討論 59
4-1 實驗試片命名與條件 59
4-2 MOS電容器電性特性分析 61
4-2.1使用釕作為金屬電極閘極材料 62
4-2.2使用鉭作為金屬電極閘極材料 63
4-3 MOS電容器漏電流特性 68
4-3.1使用釕作為金屬電極閘極材料 69
4-3.2使用鉭作為金屬電極閘極材料 70
4-4 HRTEM疊層結構分析 74
4-4.1使用釕作為金屬電極閘極材料 75
4-4.2使用鉭作為金屬電極閘極材料 77
4-5 XPS縱深分析 80
4-5.1 TiOx/HfOx/Si之XPS縱深分析 81
4-5.2 Ru/TiOx/HfOx/Si之XPS縱深分析 84
4-5.3 Ta/TiOx/HfOx/Si之XPS縱深分析 90
4-5.4 TiOx/HfOx/Si、Ru/TiOx/HfOx/Si與Ta/TiOx/HfOx/Si之XPS縱深分析比較 96
第五章 結論 105
參考文獻 107

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