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研究生:姜安璟
研究生(外文):An-JiingChiang
論文名稱:一維及二維之一階段排序器硬體設計
論文名稱(外文):Hardware Implementation of 1-D and 2-D One-Phase Sorted Rank Filter
指導教授:陳培殷陳培殷引用關係
指導教授(外文):Pei-Yin Chen
學位類別:碩士
校院名稱:國立成功大學
系所名稱:資訊工程學系碩博士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2012
畢業學年度:100
語文別:英文
論文頁數:42
中文關鍵詞:硬體字級一階段排序器
外文關鍵詞:hardware architectureword-levelone-phaserank filter
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在影像處理相關議題中,為了處理受雜訊干擾的影像,許多中值、排名濾波器,甚至排序器因而被提出。其中的排序器除了處理二維影像之外,又可以被應用在任何需要進行排序的演算法之中。此外,在實際的應用當中,去除影像雜訊可能需要利用硬體實作來達到即時處理的目的。為達成上述目標,本論文設計並實作一維及二維的排序器硬體電路。
本論文排序的方法是使用插入排序法;硬體架構則是利用字級概念實作出一個基本模組,再將N個基本模組串接成所需要的排序器架構。一維架構是假設每個單位時間內會刪除一個最舊值與插入一個新進值;而二維架構則是每個單位時間內會刪除三個最舊值與插入三個新進值,在這樣的假設與使用情況下,我們設計實作出一維及二維的硬體架構,讓每個單位時間內排序器中所儲存的值皆是由大到小完成排序的陣列。另外,針對一維硬體架構,我們也設計一個軟體IP產生器來彈性產生不同濾波視窗大小與位元寬度的排序器電路。
我們利用Verilog硬體描述語言撰寫所提出的一維與二維字級排序器硬體架構,並利用Altera Quartus來驗證其正確性。由實驗數據得知,我們所提出的一維與二維字級排序器硬體架構可在一階段內輸出正確值,且具有重複使用先前輸入值的重要優點。

In image processing, we often handle the noisy image by using median or rank filter, or even a sequencer (sorted filter). Sequencer is not only capable of processing 2-dimensional image but also applicable to any algorithms which need sort. Moreover, hardware implementation is able to increase the speed of the system.
This paper proposes hardware architecture of 1-dimensional and 2-dimensional sorted rank filter. Their circuits process the input samples sequentially in word-level manner. At each clock cycle, they only need to put the input sample in the exact position for the purpose of maintaining the sorted result of the samples. This accomplishes the reuse concept. Unlike existing 1-dimensional or 2-dimensional filter implementations, our proposed methods consider the variable values of deletion and insertion to realize 1-dimensional and 2-dimensional architecture. In addition, 1-dimensional architecture can be extended to various sizes by using a software IP generator.
We utilize Verilog and Altera Quartus to implement and verify our 1-dimensional and 2-dimensional circuits respectively. Both the 1-dimensional and 2-dimensional architectures have linear complexity, minimal latency, and one-phase processing procedure. The experiments also show high frequency and high throughputs of our designs.

摘要 IV
Abstract V
誌謝 VI
表目錄 VIII
圖目錄 IX
Chapter 1 INTRODUCTION 1
Chapter 2 RELATED STUDIES 5
2.1 Histogram-based method 5
2.2 Comparator-modules method 10
2.3 Sorted-array method 13
Chapter 3 PROPOSED METHODS 17
3.1 1-dimensional architecture 18
3.2 2-dimensional architecture 23
Chapter 4 RESULTS AND COMPARISONS 28
Chapter 5 CONCLUSIONS 39
Chapter 6 FUTURE WORKS 40
REFERENCES 41

[1]Vasily G. Moshnyaga and Koji Hashimoto (2009), “An Efficient Implementation of 1-D Median Filter, IEEE International Midwest Symposium on Circuits and Systems, Aug.
[2]S.A. Fahmy, P.Y.K. Cheung and W. Luk (2009), “High-throughput one-dimensional median and weighted median filters on FPGA, IET Comput. Digit. Tech., Vol. 3, Iss. 4, pp. 384-394.
[3]Takuya Yamamto and Vasily G. Moshnyaga (2009), “A New Bit-Serial Architecture of Rank-Order Filter, IEEE International Midwest Symposium on Circuits and Systems, Aug.
[4]XU Da-peng and LI Cong-shan (2006), “Design of Median Filter for Digital Image Based on FPGA, Chinese Journal Of Electron Device, Vol. 29, No. 4, Dec. (In Chinese)
[5]Yan Lu, Ming Dai, Lei Jiang and Shi Li (2010), “Sort Optimization Algorithm of Median Filtering Based on FPGA, IEEE International Conference on Machine Vision and Human-machine Interface, April.
[6]Chang Choo and Punam Verma (2008), “A Real-Time Bit-Serial Rank Filter Implementation Using Xilinx FPGA, Real-Time Image Processing, pp. 68110F-1-8.
[7]Dragana Prokin and Milan Prokin (2009), “Low Hardware Complexity Pipelined Rank Filter, IEEE International Midwest Symposium on Circuits and Systems, Aug.
[8]R. Roncella, R. Salemi, and P. Terreni (1993), “70-MHZ 2μm CMOS Bit-Level Systolic Array Median Filter, IEEE J.Solid-State Circ., vol. 28, no. 5, pp. 530-536.
[9]C-T. Chen, L-G Chen, J-H. Hsiao (1996), “VLSI Implementation of A Selective Median Filter, IEEE Trans. Consumer Electronics, vol. 42, no. 1, pp.34-42.
[10]M. Karaman, L. Onural, and A. Atalar, “Design and Implementation of A General-Purpose Median Filter Unit in CMOS VLSI, IEEE J.Solid-State Circ., vol. 25, no. 2, pp. 505-513.
[11]C. Lee, Hsieh, P. and Tsai, J. (1994), “High-Speed Median Filter Designs Using Shiftable Content-Addressable Memory, IEEE Trans. Circ. Syst. Video Technol. vol. 4, no. 6, pp. 544-549.
[12]G.R. Arce and P.J. Warter (1984), “A Median Filter Architecture Suitable for VLSI Implementation, Proc. the 23rd Annual Allerton Conf. Comm. Control Computing, pp. 172-181.
[13]I. Hatirnaz, F.K. Gurkaynak, and Y. Leblebici (2000), “A Compact Modular Architecture for The Realization of High-Speed Binary Sorting Engines Based on Rank Ordering, Proc. IEEE Int. Conf. Circuits and Systems, vol. 4, pp. 685-688.
[14]A Hiasat, O. Hasan (2003), “Bit-Serial Architecture for Rank Order and Stack Filters, Integration, the VLSI Journal, vol. 36, is. 1-2, pp. 3-12.
[15]V.A. Pedroni (2004), “Compact Hamming-Comparator-Based Rank Order Filter for Digital VLSI and FPGA Implementations, IEEE Int. Symp. on Circuits and Systems, vol. 2, pp. 585-588.

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