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研究生:李冠輝
研究生(外文):Kuan-HuiLi
論文名稱:使用整數線性規劃法降低負偏壓不穩定性效應及漏電流
論文名稱(外文):An ILP-based Approach for Simultaneous NBTI and Leakage Reduction
指導教授:林英超
指導教授(外文):Ing-Chao Lin
學位類別:碩士
校院名稱:國立成功大學
系所名稱:資訊工程學系碩博士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2012
畢業學年度:100
語文別:英文
論文頁數:43
中文關鍵詞:整數線性規劃法負偏壓不穩定性傳輸閘漏電流
外文關鍵詞:ILPNBTITGLeakage Power
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負偏壓不穩定性(Negative Bias Temperature Instability NBTI)會隨著運作時間而造成PMOS元件的速度下降,導致整個電路速度不符合設計需求,因此NBTI逐漸成為電路設計中主要的可靠度議題。 同時在奈米層級設計中,降低漏電流 (Leakage Power)的消耗也是主要的設計目標。 在本篇論文中,我們使用傳輸閘 (Transmission Gate TG)的技術來減緩NBTI所造成的電路速度變慢和漏電流的消耗。我們提出了整數線性規劃法(ILP),來選擇最佳的電路輸入值(input vector)並有效減少NBTI效應和漏電流。 我們也提出了一個Virtual Input Pin (VIP)技術,來增加我們的input vector對大型電路的控制能力,並結合了整數線性規劃的方法,來減緩漏電流的問題。 這個方法主要是針對critical paths來降低NBTI效應對電路造成的速度減緩,並針對non-critical paths降低漏電流。 我們使用C++和ILP Solver實作成EDA tool,可以運用在現有的IC設計流程中來減少電路老化並降低漏電流。
實驗結果顯示,我們使用TG和Virtual Input Pin的技術可以達到51.18% 電路延遲的改善,60.04%漏電流的改善,而且只增加2.31%面積。 除此之外,由於false paths不能被input vector所啟動,所以在false paths上不會發生時間違反條件限制(timing violation)。 因此,我們不考慮這些false paths並只針對sensitizable paths來做最佳化,結果顯示,依照不同電路,最多可以再降低13.26%的延遲時間,而且面積平均再降低0.39%,漏電流平均再改善了3.30%。

NBTI (Negative Bias Temperature Instability), which can degrade the switching speed of PMOS transistors, has become a major reliability challenge. Meanwhile, reducing leakage consumption is a major design goal in the nanometer era. In this paper, we use a transmission gate-based technique to mitigate NBTI degradation and leakage power consumption. We purpose an Integer Linear Programming-based (ILP-based) formulation to choose an input vector that effectively reduces both the NBTI effect and leakage. We also propose a novel virtual input pin (VIP) technique to increase the controllability of an input vector that can be integrated in the ILP formulation to improve the leakage reduction. The proposed formulation and technique can minimize the NBTI degradation on the critical path and leakage power on the non-critical path. We use C++ and ILP Solver to implement as an EDA tool which can be used in IC design flow to mitigate NBTI degradation and leakage power consumption.
Simulation results show that combining the transmission gate and virtual input pin techniques can achieve 51.18% delay improvement and 60.04% leakage power improvement with only 2.31% area overhead. In addition, since false paths are not activated by input vectors, no timing violation will occur on these paths. By removing the false path, the degradation and leakage reduction can achieve additional 0.34% to 13.26% delay improvement, 0.39% area reduction, and 3.30 % leakage power reduction.

中文摘要 ................................................................................................... i
ABSTRACT ............................................................................................... ii
誌謝 ......................................................................................................... iii
CONTENTS .............................................................................................. iv
LIST OF TABLES ...................................................................................... vi
LIST OF FIGURES ................................................................................... vii
Chapter 1 Introduction ............................................................................... 1
1.1 Paper Contribution ............................................................................... 4
Chapter 2 PRELIMINARIES ....................................................................... 6
2.1 Gate Replacement for Leakage and NBTI Mitigation. ............................... 6
2.2 Transmission Gate-based Technique for NBTI/Leakage optimization ..........7
2.3 NBTI Modeling ..................................................................................... 8
2.4 Sensitizable Paths vs. False Paths ...................................................... 10
2.5 Timed Automatic Test Pattern Generation ............................................ 12
Chapter 3 METHODOLOGY ...................................................................... 15
3.1 Virtual Input Pin ................................................................................. 15
3.2 Objective Function in ILP formulation .................................................... 16
3.2.1 Increased Delay Formulation for an NAND Gate ................................. 18
3.3 Constraints in ILP formulation .............................................................. 19
3.3.1 Path Delay Constraint ..................................................................... 19
3.3.2 Logic Constraint .............................................................................. 20
3.3.3 Area Constraint ............................................................................... 21
3.4 Formulation for Inserted TG ................................................................ 21
3.5 Method to Identify Sensitizable Path ................................................... 24
3.5.1 Tracing sensitizable paths activated by a input vector ......................... 24
3.5.2 Efficiently Identifying Sensitizable Paths ........................................... 25
3.5.3 Guaranteeing Full Coverage of Sensitizable Paths ............................. 26
Chapter 4 SIMULATION FRAMEWORK AND EXPERIMENTAL SETUP ....... 29
Chapter 5 EXPERIMENTAL RESULTS ...................................................... 31
5.1 Delay Improvement ............................................................................ 31
5.2 Leakage Improvement .........................................................................34
5.3 Sensitizable Paths ............................................................................. 35
5.4 Comparing TG and GR ........................................................................ 38
Chapter 6 CONCLUSIONS ....................................................................... 40
Chapter 7 REFERENCES ........................................................................ 41

[1]D.R. Bild, G.E. Bok and R.P. Dick, “Minimization of NBTI Performance Degradation Using Internal Node Control, in Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 148-153, 2009.

[2]X. Chen, Y. Wang, Y. Cao, Y. Ma, and H. Yang, “Variation-Aware Supply Voltage Assignment for Simultaneous Power and Aging Optimization, in Transaction on Very Large Scale Integration (TVLSI) Systems, pp. 1-5, 2011.

[3]M. DeBole, K. Ramakrishnan, V. Balakrishnan, W. Wang, H. Luo, Y. Wang, Y. Xie, Y. Cao and N. Vijaykrishnan, A Framework for Estimating NBTI Degradation of Microarchitectural Components, in Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 455-460, 2009.

[4]F. Firouzi, S Kiamehr, and M. Tahoori, A Linear Programming Approach for Minimum NBTI Vector Selection, in Great Lakes Symposium on VLSI (GLSVLSI), pp. 253-258, 2011.

[5]J. P. Halter and F. N. Najm, “A Gate-Level Leakage Power Reduction Method for Ultra-Low-Power CMSO Circuits, in Custom Integrated Circuits Conference (CICC), pp. 475-478, 1997.

[6]IBM ILOG CPLEX Optimizer, academic version linear programming solver. Available at http://www-1.ibm.com/software/integration/optimization/cplex-optimizer/

[7]Y.-M. Kuo, Y.-L. Chang, S.-C. Chang, “Efficient Boolean Characteristic Function for Timed Automatic Test Pattern Generation, in Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 417-425, 2009.

[8]N. Kimizuka, T. Yamamoto, T. Mogami, K. Yamaguchi, K. Imai and T. Horiuchi, The impact of bias temperature instability for direct-tunneling ultra-thin gate oxide on MOSFET scaling, in Symposium on VLSI Technology, Digest of Technical Papers, pp. 73-74, 1999.

[9]C.-H. Lin, I.-C. Lin and K.-H. Li, “TG-based Technique for NBTI Degradation and Leakage Optimization, in International Symposium on Low Power Design on Electronics (ISLPED), pp. 133-138, 2011.

[10]P. C. McGeer and R. K. Brayton, “Integrating Functional And Temporal Domains in Logic Design, Kluwer Academic Publishers, 1991.

[11]S.R. Naidu and E.T.A.F. Jacobs, “Minimizing stand-by leakage power in static CMOS circuits, in Design, Automation and Test in Europe Conference (DATE), pp. 370-376, 2001.

[12]NanGate Open Cell Library. Available at https://www.si2.org/openeda.si2.org/projects/nangatelib/

[13]Personal communication with Dr. Anthony Oates, Director of Technology Reliability Physics Departments, Taiwan Semiconductor Manufacturer Company, May 2012.

[14]Predictive Technology Model (PTM) and NBTI Model. Available: http://www.eas.asu.edu/~ptm

[15]J. Srinivasan, S.V. Adve, P. Bose and J.A. Rivers, The Impact of Technology Scaling on Lifetime Reliability, in Dependable Systems and Networks (DSN), pp. 177-186, 2004.

[16]W. Wang, S. Yang, S. Bhardwaj, S. Vrudhula, F. Liu and Y. Cao, The Impact of NBTI Effect on Combinational Circuit: Modeling, Simulation, and Analysis, in Transaction on Very Large Scale Integration (TVLSI) Systems, pp. 173-183, 2010.

[17]Y. Wang, H. Luo, K. He, R. Luo, H. Yang and Y. Xie, “Temperature-aware NBTI modeling and the impact of input vector control on performance degradation, in Design, Automation & Test in Europe Conference (DATE), pp. 1-6, 2007.

[18]Y. Wang, X. Cheng, W. Wang, V. Balakrishnan, Y. Cao, Y.Xie, and H. Yang, “On the Efficacy of Input Vector Control to Mitigate NBTI Effects and Leakage Power, in International Symposium on Quality Electronic Design (ISQED), pp. 19-26, 2009.

[19]Y. Wang, X. Chen, W. Wang, Y. Cao, Y. Xie and H. Yang, Leakage Power and Circuit Aging Cooptimization by Gate Replacement Techniques, in Transaction on Very Large Scale Integration (TVLSI) Systems, pp. 615-628, 2010.

[20]K.-C. Wu, D. Marculescu, Aging-aware Timing Analysis and Optimization Considering Path Sensitization, in Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 1-6, 2011.

[21]Y. Ye, S. Borkar and V. De, “A New Technique for Standby Leakage Reduction in High-Performance Circuits, in Symposium on VLSI Circuits, Digest of Technical Papers, pp. 40-41, 1998.

[22]L. Yuan and G. Qu, “Enhanced Leakage Reduction Technique by Gate Replacement, in Design Automation Conference (DAC), pp. 47-50, 2005.

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