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研究生:許嘉麟
研究生(外文):Chia-LinHsu
論文名稱:化學機械研磨應用於先進內連線缺陷與可靠度之研究
論文名稱(外文):Defect and Reliability Studies of Chemical Mechanical Polish Applications in Advanced Interconnects
指導教授:彭洞清
指導教授(外文):Dung-Ching Perng
學位類別:博士
校院名稱:國立成功大學
系所名稱:微電子工程研究所碩博士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2012
畢業學年度:100
語文別:英文
論文頁數:163
中文關鍵詞:分子層沉積鎢二硼烷銅化學機械研磨銅金屬導線銅表面粗糙度缺陷直接研磨電化學電子遷移失效模式電鍍鏽蝕腐蝕多孔性的低介電常數材料化學機械研磨後清潔時間取決之介電崩潰鎢化學機械研磨
外文關鍵詞:ALD WB2H6Cu CMPCu interconnectCu roughnessdefectdirect polishelectrochemistryelectro-migrationEMfailure modegalvanic corrosionporous low-kpost-CMP cleantime-dependent dielectric breakdownTDDBWCMP
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Abstract (in Chinese) (II)
Abstract (in English) (V)
Contents (IX)
Figure Captions (XIII)

Chapter 1 Introduction
§ 1.1 Motivation 1
§ 1.2 Thesis Organization 3
§ References 5

Chapter 2 Theory, Literature reviews and Motivations
§ 2.1 Requirements for Planarization 6
2.1.1 CMP Background 7
2.1.2 CMP Operations and Tool Configurations 7
2.1.3 CMP Performance Evaluation 8
2.1.3.1 Material Removal Rate and Non-uniformity 9
2.1.3.2 Planarization Capability 10
2.1.4 CMP Applications in Microelectronics 11
2.1.4.1 Front End of Line (FEOL) Applications 12
2.1.4.2 Middle of Line (MOL) Applications 14
2.1.4.3 BEOL End of Line (BEOL) Application 15
§ 2.2 Contact Formation and Its difficulties 16
§ 2.3 Corrosion 19
2.3.1 Corrosion Reaction 19
2.3.2 Corrosion Potentials and Currents 19
2.3.3 Galvanic corrosion 21
§ 2.4 BEOL Overview 22
2.4.1 BEOL introduction 22
2.4.2 RC Delay 24
2.4.3 Low-k dielectric materials 25
2.4.4 Cu interconnect integration scheme 28
§ 2.5 Reliabilities of Cu Interconnects 30
2.5.1 Electromigration 31
2.5.2 Stress Migration 33
2.5.3 Time Dependent Dielectric Breakdown (TDDB) 33
2.5.4 Reliability Statistics 36
2.5.5 Acceleration Models 37
§ 2.6 Summary 39
§ References 56

Chapter 3 Experimental Procedures and Techniques
§ 3.1 Wafer preparations 62
3.1.1 Contact loop wafers 62
3.1.2 BEOL loop wafers 63
§ 3.2 CMP process tools 63
3.2.1 WCMP 63
3.2.2 Cu CMP 64
§ 3.3 Analytic Techniques 64
3.3.1 Electrochemical Measurements 64
3.3.2 Atomic Force Microscopy (AFM) 65
3.3.3 Scanning Electron Microscope (SEM) 67
3.3.4 Transmission Electron Microscopy (TEM) 67
3.3.5 Secondary-Ion Mass Spectrometry (SIMS) and Time of Flight Secondary-Ion Mass Spectrometry (TOF-SIMS) 68
3.3.6 Angle-resolved X-ray Photoelectron Spectroscopy (AR-XPS) 69
3.3.7 Optical Beam Induced Resistance Change (OBIRCH) 71
§ 3.4 Electrical Measurements 71
3.4.1 EM lifetime test 71
3.4.2 TDDB lifetime test 72
§ References 80

Chapter 4 Electrochemical Studies of W Corrosion for Low Resistive Contact in the 28 nm Technology Node
§ 4.1 Background and Motivations 82
§ 4.2 Wafer Preparations 84
§ 4.3 W Nucleation Layer Depositions and WCMP Process 84
§ 4.4 Analytical Methods 85
§ 4.5 Results and Discussions 85
§ 4.6 Conclusions 88
§ References 98

Chapter 5 Defect Studies of Manufacturing Feasible Porous Low-k Dielectrics Direct Polish in 45nm Technology and beyond
§ 5.1 Background and Motivations 99
§ 5.2 Wafer Preparations 99
§ 5.3 Analytical Methods 100
§ 5.4 Results and Discussions 100
§ 5.5 Conclusions 103
§ References 113

Chapter 6 TDDB and EM Studies of the Effects of Post-CMP Cleaning for L40 Direct-Polishing Porous Low K Cu Interconnects
§ 6.1 Background and Motivations 114
§ 6.2 Wafer Preparations 117
§ 6.3 Analytical Methods 118
§ 6.4 Results and Discussions 119
6.4.1 The influence of Cu surface roughness on TDDB 119
6.4.2 The influence of Cu surface roughness on EM 121
§ 6.5 Conclusions 123
§ References 134

Chapter 7 The TDDB Failure Modes and Their Engineering Studies for Porous Low-K Dielectric Direct Polish Scheme
§ 7.1 Background and Motivations 139
§ 7.2 Wafer Preparations 140
§ 7.3 Analytical Methods 140
§ 7.4 Results and Discussions 140
7.4.1 Top Interface Failure 141
7.4.2 Sidewall Failure 142
7.4.3 Bottom Corner Failure 143
§ 7.5 Conclusions 144
§ References 152

Chapter 8 Conclusions and Prospects
§ 8.1 Conclusions 153
§ 8.2 Prospects 155

Appendix A: Author’s related publication List 157
Appendix B: Author’s Vita 163


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