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研究生:陳韋廷
研究生(外文):Wei-TingChen
論文名稱:在多核心晶片上考量多重電壓源的佈局與電源線規劃
論文名稱(外文):Floorplanning and Powerplanning for a Multi-Core Chip Considering Multiple Supply Voltages
指導教授:林家民林家民引用關係
指導教授(外文):Jai-Ming Lin
學位類別:碩士
校院名稱:國立成功大學
系所名稱:電機工程學系碩博士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2012
畢業學年度:100
語文別:中文
論文頁數:44
中文關鍵詞:實體設計多重電壓源IO單元平面規劃電源線規劃
外文關鍵詞:Physical DesignMSVIO PadFloorplanningPowerplanning
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本論文主要針對可調變頻率與電壓之多核心晶片之平面規劃進行探討。為了達到低功耗的目標,本文中的晶片使用多重電壓源的方法來動態調節效能,由於多重電壓源的架構,增加了平面規劃與電源線規劃的困難度,除此之外,為了使得溫度感測器,可以確實感測到相關模組的溫度,必須將其擺放在適當的位置,這也使得實體設計的複雜度變得越來越高。為了考量多重供應電壓源的電源線規劃,在這篇論文中我們使用了電壓島的平面佈局規劃,並且為了使得晶片可以達到更佳的效能,我們根據平面規劃的結果去調整IO單元的相關擺放位置。本篇論文採用階層式架構去降低實體設計的複雜度,首先,在晶片層級時考量電壓島的平面規劃,將操作在相同電壓的模組集合在一起,以便利之後的多重電壓源規劃,並且同時調整電源相關的IO單元擺置位置。接著,進入模組層級規劃,為了使得溫度感測器可以感測到相關的模組並且同時考量效能,我們在各模組中找出最適當擺放溫度感測器的位置,並且進行最佳化擺置與繞線流程。最後,再回到晶片層級,重新調整IO單元的位置,使得它們可以擺放於相關的模組旁邊,以提升晶片的效能,並且根據平面規劃的結果來完成電源線規劃。
This thesis mainly focuses on the floorplanning for a multi-core design, whose frequency and voltage can be adjusted. In order to reduce power consumption, Multiple Supply Voltage (MSV) technique is adopted in the chip, which increases the difficulties in floorplanning and powerplanning. Besides, to enable temperature sensors to detect temperatures of associated modules precisely, they must be placed at appropriate locations inside a block, which makes physical design a tough task. To consider powerplanning for MSV, voltage island-driven floorplanning is adopted in our methodology and relative locations of IO Pads have to be adjusted according to the resulting floorplan to ensure performance of a chip. We adopt hierarchical design flow to reduce the complexity in physical design. First stage is chip-level floorplanning considering voltage islands, in which modules operated at the same voltage are clustered together to facilitate powerplanning in later stages. Moreover, the locations of power-related IO pads are adjusted at the same time. Next stage is block-level floorplanning stage. Locations of temperature sensors in a block are determined such that they can detect temperatures of associated modules without violating timing in the block. Then, placement and routing are completed. Finally, it comes back to chip-level floorplaning. To improve performance of a chip, locations of IO Pads are adjusted according to resulting floorplan to make them can be placed close to relevant modules and powerplanning is completed.
中文摘要 I
Abstract II
誌謝 IV
目錄 V
圖目錄 VII
表目錄 IX
第一章 緒論 1
1-1 研究動機 2
1-2 平面規劃 (Floorplanning) 2
1-2-1 模組層級平面規劃 (Block-Level Floorplanning) 2
1-2-2 電源線規劃 (Powerplanning) 2
1-2-3 IO Pad平面規劃 (IO Planning) 3
1-3 EDA工具簡介 3
1-4 研究貢獻 6
1-5 論文架構 7
第二章 研究背景 8
2-1 實驗晶片介紹 8
2-2 實體設計中的問題探討 11
2-2-1 電壓島 (Voltage Island) 12
2-2-2 重新排列IO Pad 13
第三章 考量多重電壓源之平面規劃 14
3-1 晶片層級平面規劃 14
3-2 模組層級平面規劃 18
3-2-1 元件的擺置 18
3-2-2 溫度感測器的擺置 20
3-3 階層式平面規劃 23
第四章 電源網路的佈局規劃 29
4-1 電源線規劃 (Power Plan) 29
4-1-1 電源環 (Power Ring) 29
4-1-2 類比IP模組的供電 32
4-2 電源網路規劃 34
4-2-1 電壓降(IR Drop)的改善流程 34
4-2-2 標準單元(Standard Cell)的供電 36
第五章 實驗結果 38
5-1 溫度感測器的擺置對核心處理器之影響 38
5-2 分析階層式平面規劃的結果 39
第六章 結論與未來展望 42
參考文獻 43

[1]IC Compiler Data Preparation Using Milkyway™ User Guide, 200906th ed.: Synopsys, June 2009.
[2]IC Compiler Design Planning User Guide, 200906th ed.: Synopsys, June 2009.
[3]IC Compiler Commands, 200906th ed.: Synopsys, June 2009.
[4]IC Compiler Constraints Format Application Note, 200906th ed.: Synopsys, June 2009.
[5]IC Compiler Implementation User Guide, 200906th ed.: Synopsys, June 2009.
[6]IC Compiler Low-Power Flow User Guide, 200906th ed.: Synopsys, June 2009.
[7]IC Compiler Quick Reference, 200906th ed.: Synopsys, June 2009.
[8]IC Compiler Technology File and Routing Rules, 200906th ed.: Synopsys, June 2009.
[9]IC Compiler Timing Constraints and Optimization User Guide, 200906th ed.: Synopsys, June 2009.
[10]IC Compiler UPF Library Preparation Application Notes, 200906th ed.: Synopsys, June 2009.
[11]IC Compiler Zroute User Guide, 200906th ed.: Synopsys, June 2009.
[12]Cadence Encounter User Guide.
[13]Cadence Encounter Menu Reference.
[14]建立SoC全晶片電力線規劃設計流程.: 工業技術研究院.
[15]建立SoC全晶片SI分析驗證流程.: 工業技術研究院.
[16]Cell-Based IC Physical Design and Verification with SOC Encounter Training Manual.: CIC.
[17]Cell-Based IC Physical Design and Verification with IC Compiler Training Manual.: CIC.
[18]Timing and power sign-off with Prime Time Training Manual.: CIC.
[19]Logic Synthesis with Design Compiler Training Manual.: CIC.
[20]Astro User Guide, 200303rd ed.: Synopsys, March 2003.
[21]Qiang Ma and Evangeline F. Y. Young, “Voltage Island-Driven Floorplanning, ICCAD, pp. 644-649, Nov 2007.

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