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研究生:李玉雲
研究生(外文):Yu-YunLee
論文名稱:利用統計方法合成具有高變異抵抗網格以建立低功率時鐘網路
論文名稱(外文):A Statistic Approach to Synthesis High Variation-Tolerant Mesh for Constructing Low Power Clock Networks
指導教授:林家民林家民引用關係
指導教授(外文):Jai-Ming Lin
學位類別:碩士
校院名稱:國立成功大學
系所名稱:電機工程學系碩博士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2012
畢業學年度:100
語文別:英文
論文頁數:52
中文關鍵詞:時鐘網路合成時鐘網格統計基礎方法
外文關鍵詞:clock network synthesisclock meshstatistical based approach
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  • 收藏至我的研究室書目清單書目收藏:0
由於時鐘網格的高製程變異抵抗能力,現在時鐘網格是一個廣泛被運用在高效能同步超大型積體電路的時鐘網路結構。由於網格結構將會導致更多的電容使用,基於網格結構的時鐘網路與使用樹狀結構的時鐘網路相比有交多的功耗。因此,我們提出了一種統計方法來合成為一個網格(簡稱SSM)並使用於低功耗時鐘網絡上。在這篇論文中,提出統計方法確定一個良好的網格尺寸,利用電容分布為基礎,以實現所需的時鐘歪斜的約束。相比於在[19][26] 中利用切割的方式,基於統計的方法可以達到同樣的歪斜的約束。更重要的是,它是有效的,一般情況下,它可以應用到任意設計。此外,本文還提出了一個很好的時鐘網絡的拓撲結構,它集成了一個小的平衡二元樹非均勻時鐘網,以減少在底部網格的電容,以及頂部的時鐘樹。相比[19][26],這是兩個ISPD'10時鐘網絡的合成網狀結構競賽的優勝隊伍,他們的方法產生的時鐘網絡SSM的約1.51和2.36比上所提供的基準比賽。此外,SSM是非常有效的,它只需要26.81秒,平均時鐘網絡建設。
Due to its high tolerance to process-variation, clock mesh is a widely used structure in a clock network for high performance synchronous VLSI designs. Since mesh structure induces more capacitance, the mesh based clock network usually consumes more power than the tree based clock network. Therefore, we propose a Statistical approach to Synthesis a Mesh (SSM for short) for low power clock networks. In this thesis, a statistical approach is first proposed to determine a good mesh size based on sink capacitance distribution to achieve required clock skew constraint. Compared to the partition based approach [19] and [26], the statistical based method can achieve the same skew constraint using less wirelength in the resulting mesh. More importantly, it is efficient and general, which can be applied to an arbitrary design. In addition, this thesis also proposes a good clock network topology, which integrates a small balanced binary tree with a non-uniform clock mesh, to reduce capacitance in the bottom-level mesh as well as in the top-level clock tree. Compared to [19] and [26], which are two winning teams in the ISPD’10 Clock Network Synthesis Contest using the mesh structure, the clock networks generated by their approaches are about 1.51 and 2.36 larger than SSM on the benchmarks provided by the contest. Besides, SSM is very efficient, and it only requires 26.81 sec to construct a clock network in average.
摘 要 c
ABSTRACT i
誌 謝 ii
List of Figures v
Chapter 1 Introduction 7
1.1 Motivation 9
1.2 Our Contribution 10
Chapter 2 Review of Different Clock Architectures and Problem Formulation 11
2.1 Review of Common Clock Distribution Architectures 11
2.1.1 Single-Path Networks 12
H-Tree 12
Clock Tree 13
2.1.2 Multiple-Path Networks 14
Cross-Link 14
Clock Mesh 15
2.1.3 Comparison of Clock Distribution Architectures 16
2.2 Our Mesh Architecture 17
2.3 Problem Formulation 18
Chapter 3 Bottom-Level Mesh Construction 19
3.1 Overview of Our Algorithm 19
3.2 Mesh Size Determination 21
3.2.1 Problems of Previous Works 21
3.2.2 Mesh Size Determination 23
3.2.3 Consideration of Extreme Case 26
3.3 Mesh Buffer Insertion 29
3.4 Partial Segment Moving 33
Chapter 4 Experimental Result 36
4.1 Experimental Result for ISPD contest Benchmark 36
4.2 Experimental Result for Additional Extreme Cases 42
Chapter 5 Conclusions 49
Bibliography 50


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