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研究生:林宏益
研究生(外文):Hung-YiLin
論文名稱:高線性BiCMOS取樣與保持電路
論文名稱(外文):High Linear BiCMOS Track-and-Hold Amplifier
指導教授:賴源泰
指導教授(外文):Yen-Tai Lai
學位類別:博士
校院名稱:國立成功大學
系所名稱:電機工程學系碩博士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2012
畢業學年度:100
語文別:英文
論文頁數:86
中文關鍵詞:BiCMOS取樣與保持單增益放大器線性
外文關鍵詞:BiCMOStrack-and-holdunity-gainlinear
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在本篇論文中,我們提出了一個低功率BiCMOS擬差動取樣與保持電路的設計技術。為了提升BiCMOS擬差動取樣與保持電路的線性度,我們設計一個高線性度的單一增益放大器,並將這個元件放置於取樣與保持電路的輸入級。針對切換開關的設計上,我們選用切換式射極隨耦器(switched emitter-follower, )的架構。為了能加速切換此 ,我們設計一個快速關閉電路(fast turn-off circuit),使 能夠快速的被打開和關閉。我們利用TSMC 75 GHz fT, 0.35-μm SiGe BiCMOS製程去設計出我們所提出的架構電路。經由HSPICE軟體的模擬,在十億分之一的取樣速度且輸入訊號為58.59375 MHz的情況下,我們所提出來的無雜散動態範圍(SFDR)為55.52 dB,有效解析度為8.72位元. 整體電路的消耗功率為45 毫瓦。

為了進一步的降低BiCMOS取樣與保持電路的功率,我們設計一個低功率時脈緩衝器用來提供時脈給此BiCMOS取樣與保持電路使用。這個低功率時脈緩衝器的特點有兩個特點,第一為我們使用短路電流移除技術,把時脈緩衝器的輸出短路電流移除。因為不存在輸出短路電流,所以短路功率消耗可以被移除。第二個方法為電荷回收法,我們使用這個方法來回收部分的電荷,所以可以降低電路的動態功率消耗。

第三,在高增益差動放大器的設計上,差動放大器的共模輸出是很容易受到製程變異的影響,因此需要特別的共模控制電路去穩定輸出共模電壓的準位。在此部分中,我們提出一個高線性的共模迴授電路,並將這個元件應用於高增益差動放大器與每級1.5位元的管線式類比數位轉換器之乘2電路上。我們利用TSMC 0.35-μm CMOS製程去設計出我們所提出的架構電路。經由HSPICE軟體的模擬,我們所提出的共模控制電路較傳統的共模控制電路其線性度約改善了3.6% 。應用我們所提的共模迴授電路在管線式類比數位轉換器的乘2電路上,電路的訊號與雜訊失真比(SNDR)的變化範圍相較於傳統的乘2電路其變異程度約改善了33.87%。

This dissertation investigates track-and-hold amplifier (THA) in BiCMOS technology. we present a low power fully pseudo-differential open-loop BiCMOS track-and-hold amplifier (THA) based on the switched emitter-follower ( ). A high linear unity-gain buffer is designed to act as the input stage of THA for improving the linearity of the THA. The fast turn-off circuit is used to rapidly turn off the , so the aperture delay of the THA can be shortened. The simulations using TSMC 75 GHz fT 0.35-μm SiGe BiCMOS technology show that the proposed architecture achieves a spurious free dynamic range (SFDR) of 55.52 dB and a signal-to-noise distortion ratio (SNDR) of 54.27 dB for 58.59375 MHz input frequency at 1 GSample/s. The power dissipation is 45 mW.

In the second part, a low power two-phase CMOS buffer with short-circuit power elimination and charge reuse for driving the BiCMOS THA is proposed. The short-circuit power eliminating circuit is designed to remove the short-circuit current at the buffer’s output, which accounts for the largest portion of the short-circuit power dissipation of the CMOS buffer. The charge reuse circuit is used to reduce the output dynamic power dissipation of the two-phase buffer.

In high-gain fully-differential operational amplifier (FD op-amp) design, the output common-mode voltage of the FD op-amp is quite sensitive to process variations. It is therefore necessary to add an additional control circuit, referred to as the common-mode feedback circuit, to stabilize the output common-mode voltage at some specified voltage. In this part, we present a high linear CMOS continuous-time common-mode feedback circuit based on two differential pairs and the source degeneration using MOS transistors. Theoretical analysis and SPICE simulation results are provided to validate our proposed ideas. In addition, we present two design applications of the proposed configuration, one is the fully differential folded-cascode op-amp, the other is the Multiply-by-Two circuit which is the key component in the popular 1.5bit/stage pipelined ADC. Comparison with conventional topologies shows that the new configuration has attractive characteristics concerning their implementation in high linear analog integrated circuits.

Table of Contents
List of Tables .......................................viii
List of Figures..........................................x

CHAPTER 1 Introduction
1.1 Background and Motivation...........................1
1.1.1 High Speed Open-Loop BiCMOS Track-and-Hold
Amplifier.........................................1
1.1.2 Low Power CMOS Clock Buffer.......................3
1.1.3 CMOS Common-Mode Feedback Circuit.................5
1.2 Organization of the Dissertation..................6

CHAPTER 2 A 1-GSample/s 9-bit BiCMOS Track-and-Hold
Amplifier with High Linear Input Stage
2.1 Introduction........................................7
2.2 Circuit Design of the Proposed BiCMOS THA...........9
2.2.1 Input Buffer......................................9
2.2.2 Sampling Switch and Fast Turn-Off Circuit........11
2.2.3 Intermediate Buffer and Output Buffer............13
2.3 Simulation results.................................14
2.3.1 DC and AC Characteristics of the Proposed Input
Buffer...........................................15
2.3.2 The 1 GSample/s 9-b THA Design...................17
2.4 Summary............................................22

CHAPTER 3 Design of Low Power Two-Phase Buffer for BiCMOS
THA
3.1 Introduction.......................................23
3.2 The Proposed Charge Reuse Clock Buffer.............23
3.2.1 Short-Circuit Power Eliminating Circuit
Design...........................................23
3.2.2 Charge Reuse Circuit Design......................26
3.3 Analysis of Power Dissipations.....................28
3.3.1 Short-Circuit Power Dissipation Analysis.........29
3.3.2 Dynamic Power Dissipation Analysis...............30
3.4 Simulation results.................................36
3.4.1 Simulations of the SCPE Circuit with Output
Inverter.........................................37
3.4.2 Simulations of the Proposed Two-Phase Buffer.....38
3.5 Summary............................................46


CHAPTER 4 A Low Distortion CMOS Continuous-Time
Common-Mode Feedback Circuit
4.1 Introduction.......................................49
4.2 Nonlinearity in the DDA CMFB Circuit...............49
4.3 Topology Implementation for a High Linear CT-CMFB
Circuit............................................54
4.4 Application Examples of the LI-CMFB Circuit........58
4.4.1 The FD Folded-Cascode Op-Amp Design..............58
4.4.1.1 Dynamic Performance............................59
4.4.1.2 Device Mismatch................................63
4.4.2 The Multiply-by-Two Circuit Design...............68
4.5 Summary............................................73
CHAPTER 5 Conclusions .................................76
References..............................................78
Vita....................................................85
Publication lists.......................................86

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