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研究生:王明冬
研究生(外文):Ming-DungWang
論文名稱:65奈米後段銅製程缺陷改善研究
論文名稱(外文):The Studies of Improving Cu void in 65 nm BEoL Cu process
指導教授:張守進張守進引用關係
指導教授(外文):Shoou-Jinn Chang
學位類別:碩士
校院名稱:國立成功大學
系所名稱:電機工程學系專班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2012
畢業學年度:100
語文別:中文
論文頁數:57
中文關鍵詞:銅製程銅缺陷
外文關鍵詞:Cu processCu void
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隨著半導體科技技術快速發展,半導體元件大小持續下降,進而使得積體電路(IC)運算速度與效能持續獲得提升。為了解決積體電路運算速度在金屬內連線微縮時所遭遇到的瓶頸,以銅為導線的銅製程內連線技術,便蓬勃的發展起來,並且已經成為現今VLSI製程的主流技術。然而新產品在量產過程中,必定會遭遇到更多問題與挑戰,在後段銅製程內連線技術,因金屬薄膜沉積時的階梯覆蓋能力(step coverage capability)與填洞能力(gap fill capability)的相關問題,造成在金屬薄膜沉積時的微小缺陷,必定會對半導體元件的效能與壽命造成影響,使得晶片良率不如預期。
本論文針對如何改善在後段銅製程金屬內連線技術所遭遇到製程缺陷(Cu void)的問題,進而提升製程良率(Yield)做進一步的研究。首先利用3W1H、三階展開等分析手法作現況分析,找到問題發生的可能原因,再以各種實驗來加以驗證,確認問題發生的真正原因,再根據不同的原因,提出種種的改善對策,進而將製程最佳化及標準化,經確認後製程缺陷(Cu void)可大幅獲得改善,製程良率(Yield)也可提升至預期目標。

With the rapid development of semiconductor technology, the semiconductor device continues to shrink down, and thus make the switching speed and performance of integrated circuits (IC) continue to be promoted. Bottlenecks encountered when miniature metal connection in order to solve the switching speed of integrated circuits (IC). Copper conducting wire interconnect technology will be booming development, and has become today's VLSI process, mainstream technology. However new products’ production will encounter more problems and challenges. The metal film step coverage capability and gap fill capability will induce some issues in metal interconnect of the BEoL(Back End of Line)copper processing. Tiny Cu voids in the metal film deposition, this will definitely impact the performance and life-time of the semiconductor devices. Make the chip yield un-expected.
This thesis focuses on how to improve the process defects (Cu void) encountered in BEoL copper processing? Thereby enhance the process yield for further study. Using 3W1H、third-order expansion methods for situation analysis, to find the problem occurred may be the reasons, and then various experiments to verify, confirm the problem main reasons. According to different reasons, to put various improvement methods, and then the process can meet optimization and standardization. After significantly reduced process defect (Cu void), thus yield can also be upgraded to the expected target.

目錄
中文摘要Ⅱ
英文摘要Ⅳ
誌謝Ⅵ
目錄Ⅷ
表目錄Ⅹ
圖目錄XI
第一章Problem Statement-1
第二章Background-4
2-1.BEoL (Back End of Line) Cu process introduction-4
2-2.Cu Sputter barrier/Cu seed process introduction-4
2-3.Cu Plate process introduction-6
2-4.Cu CMP process introduction-7
2-5.L65奈米產品在Cu Sputter機台生產程式參數設定差異-8
2-6.在L65奈米的產品中,產品設計佈局差異-9
2-7.在L65奈米產品中,M2/Via1 Cu void造成良率損失-9
2-8.晶片良率異常的產品與生產機台chamber/cell關聯性-9
2-9.L65奈米產品在友廠生產機台程式的差異-9
第三章Status Analysis-27
第四章Root Cause Analysis and Verification-31
4-1.Root Cause Analysis-31
4-2.Root Cause Verification-33
第五章Corrective Action-47
第六章Effect Confirmation-50
第七章Future plan-51
參考文獻-56

[1]莊達人,VLSI 製造技術,高立圖書,(2007)。
[2]D. Edelstein, J. Heidenreich, R. Goldblatt, W. Cote, C. Uzoh, N. Lustig, P. Roper, T. McDevitt, W. Motsiff, A. Simon, J. Dukovic, R. Wachnik, H. Rathore, R. Schulz, L. Su, S. Luce, and J .Slattery, Full Copper Wiring in a sub-0.25mm CMOS ULSI Technology, Technical Digest, IEEE International Electron Devices Meeting, p.773 (1997).
[3]P. C. Andricacos, C. Uzoh, J. O. Dukovic, J. Horkans, and H. Deligianni, Damascene Copper Electroplating for Chip Interconnections, IBM J. Res. & Dev. 42, 567-574 (1998).
[4]C.Ryu,et al.,Solid State Technology,April ,p.53 (1999).
[5]B.Chin,et al.,Solid State Technology,July ,p.141 (1998)
[6]Akira Furuya, Masayoshi Tagami, Kazutoshi Shiba, Kuniko Kikuta,and Yoshihiro Hayashi, Evaluation of CVD/PVD Multilayered Seed for Electrochemical Deposition of Cu-Damascene Interconnects, IEEE TRANSACTIONS ON ELECTRON DEVICES, Vol.49 No.5, MAY (2002).
[7]P.M Vereecken, R.A. Binstead, H. Deligianni, P.C. Andricacos, IBM J. RES. & DEV. VOL. 49 NO.1 JANUARY (2005).
[8]A. C. West, S.Mayer, and J. Reid, A Superfilling Model that Predicts Bump Formation, Electrochem. & Solid-State Lett.4 , C50-C53 (2001).
[9]R. D. Mikkola, Q.T. Jiang, and B. Carpenter, Plating and Surface Finishing, March p.81 (2000).
[10]D. Blachier and J.Clark,Semiconductor internation,July ,p.229 (2000).
[11]M. Georgiadou, D. Veyret, R. L Sani, and R. C. Alkire, Simulation of Shape Evolution During Electrodeposition of Copper in the Presence of Additive, J. Electrochem. Soc.148 , C54-C58 (2001).
[12]P. Singer, Semiconductor International, May, p.73 (2000).
[13]A. E.Braun, Semiconductor International, December, p.54 (1999).
[14]S.M. Rossnagel and J. Hopwood, Appl. Phys, Lett.63, p.3285 (1993).
[15]S. Hamaguchi and S. M. Rossnagel, Liner conformality in ionized magnetron sputter metal deposition process, J. Vac. Sci. Technol. B, Vol.14, No. 4, Jul/Aug (1996).
[16]T. Taylor, T. Ritzdorf, F. Lindberg, B. Carpenter and M. LeFebvre. Solid State Technol. 41 11, p. 47-57 (1998).
[17]A. C. West, Theory of Filling High-Aspect Ratio Trenches and Vias in Presence of Additives, J .Electrochem. Soc.147 , p.227-232 (2000).
[18]H. P. Feng, M. Y. Cheng, Y. L. Wang, S. C. Chang, Y. Y. Wang, C. C. Wan, Mechanism for Cu void defect on various electroplated film conditions, Thin Solid Films 498 p56-59 (2006).
[19]K. R. Hebert, J. Electrochem. Soc. 148 , C726 (2001).
[20]李輝煌,田口方法-品質設計原理與實務,高立圖書,(2000)。

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