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研究生:葉俊宏
研究生(外文):Chun-HungYeh
論文名稱:使用先進電子束缺陷檢測設備以加速金氧化半導體製程開發
論文名稱(外文):Acceleration of CMOS process development with an advanced e-beam defect inspection system
指導教授:蘇炎坤蘇炎坤引用關係
指導教授(外文):Y.K Su
學位類別:碩士
校院名稱:國立成功大學
系所名稱:電機工程學系專班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2012
畢業學年度:100
語文別:英文
論文頁數:68
中文關鍵詞:電子束良率缺陷檢測電壓反差
外文關鍵詞:e-BeamYieldDefect inspectionVoltage Contrast
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隨著半導體新材料、新製程技術的應用以及半導體元件微小化之趨勢下,傳統缺陷檢測技術遇到了極大的挑戰。為了加速提高產品良率,新一代缺陷檢測技術必須在有限的成本之下,能夠以更快的速度和更高的靈敏度捕捉到並自動分類各種缺陷。

缺陷檢測技術主要有暗場(Dark Field)、明場(Bright Field)和電子束(e-Beam)檢查。電子束檢測以聚焦電子束作為檢測源,靈敏度最高,但是檢測速度最慢,價格最高。採用電子束檢測時,入射電子束激發出二次電子,然後通過對二次電子的收集,以呈現的圖像來解析晶圓在製程中的缺陷。機台所呈現的掃描圖像,以分析捕捉到光學檢查設備無法檢測到的缺陷。例如當CONTACT 或VIA 等HAR 結構未充分蝕刻(Contact Open)時,由於缺陷在結構底部,因此很難用暗場或明場檢測設備檢測到,但因為該缺陷會影響入射電子的傳輸,所以會形成電壓反差(Voltage Contract)影像,從而檢測到由於HAR 結構異常而影響電性的各種缺陷。此外由於檢測源為電子束,檢測結果不受某些表面物理性質例如顏色異常、厚度變化或前層缺陷之影響,因此電子束檢測技術還可用於檢測很小的表面缺陷例如柵極刻蝕殘留物等。

一般而言,影響良率的缺陷通常源自於部份或整個元件中的物理性缺陷(Physical Defects),電子束檢測也因為電子束的像素(pixel size)較光學小(約300~15nm) ,可以偵測到光學檢測無法偵測到的物理性缺陷。然而電子束檢測最為人重視的是部份或整個元件中的電性缺陷所造成的異常電流所導致的Voltage Contrast(VC)。電子束造成晶圓表面帶電,使缺陷部位出現電壓差異,影響到晶片表面二次電子逃逸率。而由此產生的圖像差異即可被偵測出。通常這類缺陷無法從光學儀器中看出,但卻可以透過電子束檢測系統發現到。尤其是在許多尖端元件中的前段製程(FEOL)。殘餘的Poly、Contact hole etch stopping、SAC hole punch-through、dielectric film mal-gap-filling spaces、 substrate 之中的缺陷、異常Ion Implant 等皆屬此類關鍵缺陷,這些缺陷都會令元件失效而對良率產生負面影響。運用傳統的量測方法來偵測這些缺陷是件極困難的。然而,一般電性量測往往只能在製程結束後才進行,其回饋的時間往往相當長。相較之下,利用電子束檢測技術不僅能縮短回饋時間,亦可有效減少確認與排除各種製程問題的學習時間,且能降低晶圓風險成本,運用電子束檢測系統FAB 或R&D 可在有問題的製程步驟後立即收集到缺陷的分佈位置、製程最佳化的回饋資料等關鍵資訊以加快開發和試產。高靈敏度(Sensitivity) 對於半導體前段製程微弱的Voltage Contrast(VC)缺陷有極高的靈敏度,如接觸窗蝕刻後的檢測有高的靈敏度。在鎢插栓接觸窗站點可以進行PMOS 接觸窗斷路與NMOS 接觸窗及其元件漏電流檢測。或可以進行表面為負電荷的電子束檢測,在鎢插栓接觸窗站點可以進行NMOS 接觸窗斷路與PMOS 接觸窗及其元件漏電流檢測。在45 奈米及以下低漏電元件開發及量產有極大的實用價值。
To achieve aggressive device scaling, introduction of new semiconductor materials and processes have made traditional defect inspection methods obsolete in meeting these new technological challenges. In order to rapidly increase product yield, new defects arising from these challenges have to be captured with new defect inspection technologies which are faster and more sensitive than their predecessors. To date, the major inspection technologies in the market included Dark Field, Bright Field and Ebeam.

The Dark Field defect Inspection technology is based on laser as its light source. It has medium sensitivity; is fast and is low cost. It is equipped with low angle detectors for detecting light rays scattering from surface defects on non-topography wafers.The Bright Field defect Inspection technology uses optical or laser light as its light source. Its sensitivity is higher than Dark Field but its speed is lower and is more costly. Its light source path of incidence and reflection to the detectors are coincident, and they are collected by high-angle detectors ( 70° ~ 90° ). Such inspectors have small pixel size ( 〈 1um ) which is good for both topography ( especially HAR structures ) and non-topography defects. Its high sensitivity is used to capture physical defects at FEOL, after resist-develop inspection ( ADI ) and after etch inspections ( AEI ).

For 65nm technology and beyond, UV/ DUV light sources and smaller pixel sizes are introduced to cater to higher sensitivity inspections. Such new inspection technologies are able to capture small defects ( as small as 20 by 40nm in dimensions ) within reasonable inspection times. Ebeam inspection uses focused electron beam as its source. It has the highest sensitivity but lowest speed. Its high sensitivity is accompanied by high cost. Such inspectors are good for both physical surface defects and electrical defects causing shorts and opens. The latter defect type is not captured by optical inspection tools.

Incident electrons fall on a wafer surface, resulting in electron avalanche and generating secondary electrons from the substrate. These secondary electrons are collected by a HMI patented annular detector and output as digital gray level images of the scanned area. From such gray level images, the different types of defects could be identified based on the voltage contrast generated through such electron interactions. For example, when contacts and vias of high aspect ratios are not fully etched; some residue will remain at the bottom of the contacts or vias. There is no path for the electrons to flow to the under-lying conductive layers and are accumulated inside the holes. Voltage contrast is generated between the top surface of the respective contacts or Vias and the substrate due to this potential difference. Using this detection method, the abnormally etched holes are separated from the normal ones. Ebeam is also good for sub-micron physical defects’ detection as it is not affected by color variations of the surface, thickness variations of incoming planar surfaces or pre-layer defects, for example gate etch residues.

eScan has high sensitivity in detecting the weak VC defects in IC Front-end process, such as in CT_AEI. In CONTWCMP, PMOS short and NMOS leakage can be detected. Or, NMOS short and PMOS leakage can be captured by inspection with obtaining the negative charge on the wafer surface in WCMP. eScan can contribute great practical value in low leakage development and production for 45nm generation or under.
Thesis Certification.....................................I
Abstract (Chinese)......................................II
Abstract (English)......................................IV
Acknowledgement (Chinese)..............................VII

Contents..................................................1
Figure Captions...........................................3
Chapter 1 Introduction....................................6
Chapter 2 Advanced e-Beam On-line Defect Detection Systems
2-1 Design of e-Beam Defect Detection Systems...........8
2-2 The theory of voltage contrast (VC)................13
2-3 Detection mechanism and digital gray level (GL)....17
2-4 Post Contact Tungsten (W) CMP (Chemical Mechanical
Planarization) e-beam inspection...................19
Chapter 3 e-Beam Application with surface positive
charging mode in CMOS MOL (Middle of the Line) process...21
3-1 The NMOS Leakage...................................21
3-2 Retrograde well implants...........................24
3-3 Intra-well isolation...............................26
3-4 Experiments and results............................28
3-4-1 Quad implants with a very small tilt angle.....28
3-4-2 Split experiment...............................30
3-4-3 Result.........................................32
Chapter 4 e-Beam Application with surface negative charging mode in CMOS MOL (Middle of the Line) process............34
4-1 VC mechanism of the PMOS Leakage Defects.........34
4-2 A special phenomenon in surface negative mode....35
4-3 Experiment and Result............................36
4-3-1 the correlation between NMOS Backs by positive
mode and NMOS DVDs by negative mode..........36
4-3-2 The Failure Mechanism Analysis of PMOS leakage
DVDs and NMOS Bit-line BVCs..................38
Chapter 5 Conclusion.....................................41
Reference................................................42
Tables and Figures.......................................45
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