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研究生:鄭貿薰
研究生(外文):Mao-HsunCheng
論文名稱:非晶矽薄膜電晶體閘極驅動電路於液晶顯示器之設計
論文名稱(外文):Design of Gate Driver Circuits for TFT-LCDs Based on a-Si:H Technology
指導教授:林志隆林志隆引用關係
指導教授(外文):Chih-Lung Lin
學位類別:碩士
校院名稱:國立成功大學
系所名稱:電機工程學系碩博士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2012
畢業學年度:100
語文別:英文
論文頁數:47
中文關鍵詞:非晶矽薄膜電晶體閘極驅動電路功率消耗
外文關鍵詞:Amorphous silicon thin-film transistorgate driver circuitpower consumption
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近年來,為了降低面板的成本並提高其整體之可靠性,使用非晶矽薄膜電晶體技術設計整合在主動式液晶顯示器驅動電路已逐漸成為主流。然而在長時間的操作或是高施加偏壓的情況下,非晶矽薄膜電晶體容易產生老化現象而造成臨界電壓上升,進而影響驅動電路的穩定性,使得面板顯示得畫面失真。
針對上述之問題,本論文提出了三個新式的閘極驅動電路,並經由模擬軟體與實際的量測結果證明所提出電路之可行性。第一個電路由十二顆非晶矽薄膜電晶體與一顆電容與六組時脈訊號所組成,特色為利用低頻率的時脈訊號,穩定輸出端點之電壓波形並改善電路的功率消耗,且施加穩壓電晶體閘極-源極反向偏壓,以抑制電晶體臨界電壓之變異性。實驗結果證明,與在直流偏壓的情況相比,施加反向偏壓的機制可使得臨界電壓變異之情況改善20.35%,且與傳統閘極驅動電路比較,可節省47.02%的功率消耗,且此電路可在100 ◦C 穩定地操作超過240個小時,其輸出波形充、放電達最高與最低電位所需之時間分別是7.8 μs與5 μs。第二個閘極驅動電路為十顆非晶矽薄膜電晶體、一顆電容與六組時脈訊號之架構。此電路針對了第一個電路做改進,為了進一步降低功率消耗,減少了薄膜電晶體的使用數量與尺寸,並可節省約17%的佈局面積。模擬結果顯示,此電路能夠有效地穩定輸出波形,其充、放電達最高與最低電位所需之時間分別是5.5 μs與4.2 μs。第三個閘極驅動電路由九顆非晶矽薄膜電晶體、二顆電容與三組時脈訊號構成,此電路改進了前兩個電路利用過多的時脈訊號,並使用了交流驅動的方式改善電晶體臨界電壓上升之現象,可使得電路的輸出端點無浮接之現象;另外,利用設計以調變穩壓電晶體的閘極偏壓,更可以進一步減緩電晶體臨界電壓的變異性,且降低功率之消耗。根據實驗結果,此電路可在60 ◦C下穩定地操作240個小時以上,輸出波形充、放電達穩態的時間分別為6.4 μs與5.2 μs。

In recent years, using hydrogenated amorphous thin-film transistors (a-Si:H TFTs) to design driver circuits for active-matrix liquid crystal displays (AMLCDs) has attracted a large amount of attention because of the reduction in cost of fabrication and the increase in reliability. However, the severe threshold voltage (VTH) shift of a-Si:H TFTs which is caused by bias stress in addition to charge trapping and defect-state creation under long-term operation leads to the instability of driver circuits and subsequently affects the image quality of AMLCDs.
This thesis proposes three gate driver circuits for which both the feasibility is verified through the Hspice simulator and the stability is proven by experimental results. The first gate driver circuit, composed of twelve a-Si:H TFTs, a capacitor and six clock signals, uses two opposite-phase and low-frequency clock signals to stabilize the row lines against floating and improve the power consumption. Furthermore, the reverse-bias scheme is applied to the gate-to-source voltage (VGS) of the pull-down TFTs to improve the VTH shift. According to the experimental results, the VTH variation is improved by 20.35% compared to that of TFTs under DC bias, and the power consumption is reduced by 47.02% relative to the conventional gate driver circuit. Additionally, this circuit can be operated over 240 hours at 100◦C, and the rising time (TRISE) and falling time (TFALL) of the output waveform are 7.8 μs and 5 μs, respectively. The second gate driver circuit, consisting of ten TFTs, one capacitor and six clock signals, continues with the concepts of the first gate driver circuit. Also, the number of components is lessened to further decrease the power consumption and reduce the layout area by approximately 17% compared to the first gate driver circuit. Based on the simulation results, the TRISE and TFALL are 5.5 μs and 3.8 μs, respectively. The third gate driver circuit is composed of nine TFTs, two capacitors and three clock signals. The new circuit reduces the number of clock signals and utilizes the AC-driving method to suppress the VTH shift of TFTs and prevent the row lines from floating. Moreover, modulating the gate bias of the pull-down TFTs can reduce power dissipation and further ameliorate the VTH shift to ensure the stability of the proposed circuit under long-term operation. Experimental results indicate that this circuit can operate stably over 240 hours at 60◦C. The TRISE and TFALL of the output waveform are 6.4 μs and 5.2 μs, respectively.

Chinese Abstract.....……………………………………………………………..............I
English Abstract……….…….………………………………..……………………….III
Acknowledgements……………………………………………………………………V
Contents……………………......……………………………………………………...VI
Table Captions……………………………………………………………....……….VIII
Figure Captions………………………………...…………….…………………....…..IX
Chapter 1 Introduction
1.1. Background………………………………………………………………………1
1.2. Motivation and Previous Researches……….……………………………………4
1.3. Thesis Organization……………..………………………………………………8
Chapter 2 Power Consumption Ameliorating for Integrated Gate Driver Circuit with Low-Frequency Clock
2.1. Previous Gate Driver Circuits on Glass………………...…………………..……9
2.2. Circuit Schematic and Operation……………………………………………….10
2.3. Results and Discussions...………………………………………………………12
2.4. Summary………………………………………………………………..………13
Chapter 3 Low-Power Gate Driver Circuit with Threshold Voltage Shift Recovery Scheme
3.1. Consideration on Power Consumption of the Previous Works…………………18
3.2. Circuit Schematic and Operation…………………...…………………………..19
3.3. Simulation and Experimental Results………………………………..…………21
3.4. Summary………………………………………………………………………..22
Chapter 4 Highly Reliable Integrated Gate Driver Circuit for Large TFT-LCD Applications
4.1. Issues of the Previous Works....…………………………………………………30
4.2. Circuit Schematic and Operation………………………………………….……31
4.3. Results and Discussions…………….………………………………………..…33
4.4. Summary………………………………………………………………………..34
Chapter 5
5.1 Conclusions……………...……………………………………………………….39
5.2 Future works…..................……………………………………………………….40
References…....................................................................................................................42
Publication List…..........................................................................................................47

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