跳到主要內容

臺灣博碩士論文加值系統

(34.204.180.223) 您好!臺灣時間:2021/08/05 23:55
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果 :::

詳目顯示

: 
twitterline
研究生:陳怡秀
研究生(外文):Yi-SiouChen
論文名稱:適用於電子系統層級之具有能量感知的匯流排通訊架構探勘
論文名稱(外文):A Framework for Energy-Aware Bus-based Communication Architecture Exploration at Electronic System Level
指導教授:邱瀝毅
指導教授(外文):Lih-Yih Chiou
學位類別:博士
校院名稱:國立成功大學
系所名稱:電機工程學系碩博士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2012
畢業學年度:100
語文別:英文
論文頁數:132
中文關鍵詞:低功率設計空間探勘晶片通訊架構設計電子系統層級系統階層效能評估
外文關鍵詞:Low PowerDesign Space ExplorationOn-Chip Communication ArchitectureElectronic System LevelSystem-Level Performance Estimation
相關次數:
  • 被引用被引用:0
  • 點閱點閱:131
  • 評分評分:
  • 下載下載:7
  • 收藏至我的研究室書目清單書目收藏:0
隨著製程技術持續的進步與在產品功能上日益增加的需求,電子系統層級合成方法在維持設計生產力上備受看好。合成任務包含運算與通訊資源的配置、鏈結與排程,而這些任務的設計與探勘必須能夠在不同的抽象設計層級被進行。由於,如今精密產品漸採用多核系統架構設計,這將使得處理器間的資料傳輸劇烈地增加,造成系統效能下降與功耗上升。由此觀之,設計者需更謹慎地構思通訊架構,使其運算與溝通單元們能在有限的系統資源下,進行平行有效率地運作。
積極地降低功率消耗是當前發展消費性電子產品的重要趨勢。系統階層功率探勘能幫助設計者於早期設計階段診斷架構的問題,其有助於更快速地達成低功耗架構設計。本文提出了一具有能量感知的匯流排架構探勘演算法。其研發重點摘要如下:首先,此架構採用多合成任務同步分析演算法來有效率地進行「運算單元至計算硬體的鏈結」、「溝通資料至記憶體的配置」和「通訊路徑的規劃」等參數的設計。再者,快速的動態追蹤系統評估方法可提高探勘的速度與降低系統設計者在探勘過程中改建模擬模組的工作。最後,此架構結合了系統階層功率意識切割演算法,幫助設計者在早期架構設計階段進行功率管理系統的規劃。
Electronic System Level (ESL) synthesis is a promising solution for maintaining design productivity in the context of ever-increasing chip manufacturing capacities and customer demands for function-rich products. Synthesis involves the allocation of resources, and binding and scheduling for computation and communication operations at various levels of abstraction. Furthermore, demand for multi-processor systems in sophisticated products is increasing. Designers should carefully design communication architectures when the amount of data transferred among processors increases markedly and significantly reduces performance and increases power consumption.
As system complexity increases, power consumption becomes one of important factors, especially for portable products that must conserve energy. System-level power exploration has a crucial role in helping system architects examine the power consumption of product designs. This dissertation presents an energy-aware, bus-based communication architecture exploration framework that simultaneously assesses the evolution of architectural mapping and partitioning tasks. The proposed framework is flexible and sufficiently powerful for analyzing the architectures with various behavior-processing-element mapping, variable-memory mapping and channel-bus mapping. The proposed dynamic trace-driven method reduces the effort needed for system remodeling after each decision and shortens the estimation time needed for performance evaluations, thereby enhancing exploration effectiveness. Additionally, the proposed framework, which is combined with a system-level, energy-aware partitioning algorithm, is applied to identify promising implementation options when designing power-manageable systems.
CHAPTER1 INTRODUCTION............................................................................1
CHAPTER2 SYNTHESIS FRAMEWORK AT ELECTRONIC SYSTEM LEVEL.......5
2.1. Electronic System Level Synthesis.............................................................6
2.1.1 Concept of the Electronic System Level.....................................................7
2.1.2 General Synthesis Process......................................................................9
2.1.3 Definition of ESL Synthesis.....................................................................10
2.2. Application-to-Architecture Design Tasks during ESL Synthesis...................12
2.2.1 General Synthesis Tasks........................................................................12
2.2.2 Example of ESL Synthesis at Four Abstraction Levels...............................14
2.3. Schema for Design Space Exploration.......................................................16
2.4. Provocative Thoughts................................................................................17
2.4.1 Automation Tools for Model Refinement....................................................17
2.4.2 Evolutionary Algorithm for Communication Architecture Exploration.............18
2.4.3 Trace-Driven Estimation...........................................................................19
2.4.4 Limitations of Method-Sequence Exploration (MSE)...................................19
2.4.5 Power Management for ESL Synthesis.....................................................20
2.5. Summary.................................................................................................21
CHAPTER 3 RELATED WORKS......................................................................22
3.1. System-level Performance Estimation.........................................................22
3.2. System-Level Channel Exploration..............................................................24
3.2.1 Communication Synthesis and Exploration................................................25
3.2.2 Data Layout and Memory Architecture Exploration.....................................28
3.2.3 Simultaneous Tasks Exploration...............................................................29
3.3. Temporal Partition for Power Management Development...............................31
3.4. Summary.................................................................................................32
CHAPTER 4 ENERGY-AWARE COMMUNICATION ARCHITECTURE EXPLORATION DURING ESL SYNTHESIS...............................................................................33
4.1. Introduction...............................................................................................34
4.2. Target Architecture and Application Model...................................................35
4.2.1 Definition of the Architectural Model..........................................................36
4.2.2 Definition of the Application Model............................................................38
4.2.3 Granularity Assumption and Refinement....................................................39
4.3. The CESATE Framework...........................................................................40
4.3.1 Problem Definition and Assumption...........................................................40
4.3.2 Overview of the CESATE Framework.........................................................42
4.3.3 Permutation Method................................................................................48
4.3.4 Quality Measure......................................................................................51
4.3.5 Rectification Functions.............................................................................53
4.4. Summary..................................................................................................56
CHAPTER 5 TRACE-DRIVEN METHOD FOR ANALYZING ARCHITECTURAL PERFORMANCE.............................................................................................57
5.1. Introduction...............................................................................................57
5.2. Example for the Competing-for-Execution Issue............................................59
5.3. Dynamic Trace-Driven Performance Estimation Method (APDT).....................60
5.3.1 Problem Definition and Assumption...........................................................60
5.3.2 APDT Design Methodology.......................................................................60
5.3.3 Performance Analysis Procedure..............................................................62
5.4. Experimental Results................................................................................65
5.4.1 Construction of Execution Flow Graph.......................................................65
5.4.2 Platform Architectures.............................................................................66
5.4.3 Deviation between bus-functional model and APDT.....................................67
5.5. Summary.................................................................................................70
CHAPTER 6 COMMUNICATION ARCHITECTURE EXPLORATION FOR POWER MANAGEMENT SYSTEM DEVELOPMENT.......................................................71
6.1. Introduction...............................................................................................71
6.2. Bus-Based Energy-Aware Partition (BEAP)..................................................73
6.2.1 Problem Definition and Assumption............................................................73
6.2.2 BEAP Design Methodology.......................................................................74
6.2.3 Experimental Results...............................................................................75
6.3. Simultaneous Task Mapping and Energy-Aware Power Management Partition for Distributed Computation System (STMEP).........................................................76
6.3.1 Motivational Example...............................................................................76
6.3.2 Problem Definition and Assumption...........................................................77
6.3.3 STMEP Design Methodology....................................................................78
6.3.4 Experimental Results...............................................................................79
6.4. Summary..................................................................................................83
CHAPTER 7 SYSTEM-LEVEL COMPUTATION AND COMMUNICATION CO-EXPLORATION................................................................................................84
7.1. Introduction...............................................................................................85
7.2. Motivational Example.................................................................................86
7.3. Multi-Objective Simultaneous-task Architecture Exploration Algorithm (MOSTE)........................................................................................................88
7.3.1 Problem Definition and .Assumption..........................................................88
7.3.2 MOSTE Design Methodology....................................................................89
7.3.3 Two-direction Iterative Algorithm (TD-IA).....................................................92
7.3.4 Acceptance Function...............................................................................95
7.4. Experimental Results................................................................................96
7.4.1 Comparison Metrics................................................................................96
7.4.2 Pareto-Front Curve for Performance and Cost Trade-off...............................99
7.4.3 Comparisons of the MOSTE with the MSE approaches..............................100
7.5. Summary.................................................................................................102
CHAPTER 8 EFFECTIVE COMMUNICATION ARCHITECTURE EXPLORATION USING EVOLUTIONARY ALGORITHMS......................................................................103
8.1. System-Level Bus-Based Communication Architecture Exploration Using a Pseudo Parallel Algorithm (PBAES).................................................................104
8.1.1 Introduction............................................................................................104
8.1.2 Problem Definition and Assumption..........................................................105
8.1.3 PBAES Design Methodology...................................................................105
8.1.4 Experimental Results..............................................................................107
8.1.5 Summary...............................................................................................111
8.2. Multi-Mode Communication Exploration Using a Constraint Weighting Function (BAEMSs)......................................................................................................112
8.2.1 Introduction.............................................................................................112
8.2.2 Problem Definition and Assumption...........................................................113
8.2.3 BAEMSs Design Methodology..................................................................113
8.2.4 Experimental Results...............................................................................116
8.2.5 Summary................................................................................................120
CHAPTER 9 CONCLUSIONS AND FURTHER WORKS.......................................121
9.1. Conclusions of This Dissertation.................................................................121
9.2. Perspectives and Future Works..................................................................124
REFERENCES................................................................................................125
[1]F. C. Tseng, The future of semiconductor industry- a foundry's perspective, in Proc. Int. Conf. Asia and South Pacific Design Automation, 2008, pp. 558-558.
[2]The International Technology Roadmap For Semiconductors (ITRS); [Online] Available: http://www.itrs.net.
[3]Synopsys DesignWare TLM Library; [Online] Available: http://www.synopsys.com/.
[4]Texas Instruments OMAP Platform; [Online] Available: http://www.ti.com/.
[5]W. Wolf, A. A. Jerraya, and G. Martin, Multiprocessor System-on-Chip (MPSoC) Technology, IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 27, no. 10, pp. 1701-1713, Oct. 2008.
[6]G. Martin, B. Bailey, and A. Piziali, ESL Design and Verification: A Prescription for Electronic System Level Methodology, Elsevier-Morgan Kaufmann, San Francisco, CA, 2007.
[7]D. Densmore and R. Passerone, A Platform-Based Taxonomy for ESL Design, Design & Test of Computers, vol. 23, no. 5, pp. 359-374, Sept.-Oct. 2006.
[8]Forte Cynthesizer; [Online] Available: http://www.forteds.com.
[9]G. Chandra, P. Kapur, and K. C. Saraswat, Scaling trends for the on chip power dissipation, in Proc. Int. Conf. Interconnect Technology, 2002, pp. 170-172.
[10]K. Lahiri and A. Raghunathan, Power analysis of system-level on-chip communication architectures, in Proc. Int. Conf. Hardware/Software Codesign and System Synthesis, 2004, pp. 236-241.
[11]P. Lieverse, P. v. d. Wolf, E. Deprettere, and K. Vissers, A methodology for architecture exploration of heterogeneous signal processing systems, in Proc. IEEE Workshop Signal Processing Systems, 1999, pp. 181-190.
[12]L. Benini, A. Bogliolo, and G. D. Micheli, A survey of design techniques for system-level dynamic power management, IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 8, no. 3, pp. 299-316, June 2000.
[13]Synopsys System-Level Design Solutions; [Online] Available: http://www.synopsys.com/Systems/Pages/default.aspx.
[14]Carbon SoC Designer Plus; [Online] Available: http://www.carbondesignsystems.com/soc-designer-plus.
[15]Synopsys Synphony C Compiler; [Online] Available: http://www.synopsys.com/Systems/BlockDesign/HLS/Pages/SynphonyC-Compiler.aspx.
[16]Synopsys Synphony Model Compiler; [Online] Available: http://www.synopsys.com/Systems/BlockDesign/HLS/Pages/Synphony-Model-Compiler.aspx.
[17]A. Gerstlauer, C. Haubelt, A. D. Pimentel, T. P. Stefanov, D. D. Gajski, and J. Teich, Electronic System-Level Synthesis Methodologies, IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 28, no. 10, pp. 1517-1530, Oct. 2009.
[18]J. Teich, Embedded System Synthesis and Optimization, in Proc. Int. Conf. System Design Automation, 2000, pp. 9-22.
[19]L. Cai and D. Gajski, Transaction level modeling: an overview, in Proc. Int. Conf. Hardware/Software Codesign and System Synthesis, 2003, pp. 19-24.
[20]L. Cai, S. Verma, and D. D. Gajski, Comparison of SpecC and SystemC Languages for System Design, CECS, UC Irvine, Technical Report CECS-TR-03-11, May 2003.
[21]Synopsys System-Level Models; [Online] Available: http://www.synopsys.com/Systems/SLModels/Pages/default.aspx.
[22]F. Balarin, Y. Watanabe, H. Hsieh, L. Lavagno, C. Passerone, and A. Sangiovanni-Vincentelli, Metropolis: an integrated electronic system design environment, IEEE Computer, vol. 36, no. 4, pp. 45-52, April 2003.
[23]L. Cai and D. D. Gajski, Variable Mapping of System Level Design, CECS, UC Irvine, Technical Report CECS-TR-02-32, Oct. 2002.
[24]L. Cai and D. D. Gajski, Channel Mapping in System Level Design, CECS, UC Irvine, Technical Report CECS-TR-03-03, Jan. 2003.
[25]C. Zhongbo, R. Mercado, and D. T. Rover, System-level memory modeling for bus-based memory architecture exploration, in Proc. Int. Conf .Electro/Information Technology, 2009, pp. 239-244.
[26]Y. Choi, T. Kim, and H. Han, Memory layout techniques for variables utilizing efficient DRAM access modes in embedded system design, IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 24, no. 2, pp. 278-287, Feb. 2005.
[27]T. Kim and J. Kim, Integration of Code Scheduling, Memory Allocation, and Array Binding for Memory-Access Optimization, IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 1, pp. 142-151, Jan. 2007.
[28]T. S. R. Kumar, C. P. Ravikumar, and R. Govindarajan, Memory Architecture Exploration Framework for Cache Based Embedded SOC, in Proc. Int. Conf. VLSI Design, 2008, pp. 553-559.
[29]B. Kienhuis, E. Deprettere, K. Vissers, and P. V. D. Wolf, An approach for quantitative analysis of application-specific dataflow architectures, in Proc. Int. Conf. Application-Specific Systems Architectures and Processors (ASAP), 1997, pp. 338-349.
[30]M. Gries, Methods for Evaluating and Covering the Design Space during Early Design Development, Integration, the VLSI Journal, vol. 38, no. 2, pp. 131-183, Dec. 2004.
[31]D. S. Rao and F. J. Kurdahi, Hierarchical design space exploration for a class of digital systems, IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 1, no. 3, pp. 282-295, Sept. 1993.
[32]G. Snider, Spacewalker: Automated design space exploration for embedded computer systems, HP Laboratories, Palo Alto, California, Technical Report HPL-2001-220, Sept. 2001.
[33]V. Kathail, S. Aditya, R. Schreiber, B. R. Rau, D. C. Cronquist, and M. Sivaraman, PICO: automatically designing custom computers, IEEE Computer, vol. 35, no. 9, pp. 39-47, Sept. 2002.
[34]OSCI; [Online] Available: http://media.systemc.org/index.html.
[35]Accellera; [Online] Available: http://www.accellera.org/home.
[36]A. Stammermann, L. Kruse, W. Nebel, A. Pratsch, E. Schmidt, M. Schulte, and A. Schulz, System level optimization and design space exploration for low power, in Proc. Int. Symp. System Synthesis, 2001, pp. 142-146.
[37]M. Caldari, M. Conti, M. Coppola, S. Curaba, L. Pieralisi, and C. Turchetti, Transaction-level models for AMBA bus architecture using SystemC 2.0, in Proc. of Design Automation and Test in Europe Conf., 2003, pp. 26-31.
[38]W. Klingauf, R. Gunzel, O. Bringmann, P. Parfuntseu, and M. Burton, GreenBus - a generic interconnect fabric for transaction level modelling, in Proc. Int. Conf. Design Automation, 2006, pp. 905-910.
[39]R. B. Atitallah, S. Niar, S. Meftali, and J.-L. Dekeyser, An MPSoC Performance Estimation Framework Using Transaction Level Modeling, in Proc. Int. Conf. Embedded and Real-Time Computing Systems and Applications, 2007, pp. 525-533.
[40]J. Cornet, F. Maraninchi, and L. Maillet-Contoz, A Method for the Efficient Development of Timed and Untimed Transaction-Level Models of Systems-on-Chip, in Proc. of Design Automation and Test in Europe Conf., 2008, pp. 9-14.
[41]S. Pasricha, N. Dutt, and M. Ben-Romdhane, Fast exploration of bus-based on-chip communication architectures, in Proc. Int. Conf. Hardware/Software Codesign and System Synthesis, 2004, pp. 242-247.
[42]G. Beltrame, D. Sciuto, C. Silvano, D. Lyonnard, and C. Pilkington, Exploiting TLM and Object Introspection for System-Level Simulation, in Proc. of Design Automation and Test in Europe Conf., 2006, pp. 1-6.
[43]M. Tawk, K. Z. Ibrahim, and S. Niar, Multi-granularity sampling for simulating concurrent heterogeneous applications, Proc. Int. Conf. Compilers, architectures and synthesis for embedded systems, 2008, pp. 217-226.
[44]K. Lahiri, A. Raghunathan, and S. Dey, System-level performance analysis for designing on-chip communication architectures, IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 6, pp. 768-783, June 2001.
[45]T. Wild, A. Herkersdorf, and R. Ohlendorf, Performance Evaluation for System-on-Chip Architectures using Trace-based Transaction Level Simulation, in Proc. of Design Automation and Test in Europe Conf., 2006, pp. 1-6.
[46]A. D. Pimentel, L. O. Hertzbetger, P. Lieverse, P. v. d. Wolf, and E. F. Deprettere, Exploring embedded-systems architectures with Artemis, IEEE Computer, vol. 34, no. 11, pp. 57-63, Nov. 2001.
[47]A. D. Pimentel and C. Erbas, An IDF-based trace transformation method for communication refinement, in Proc. Int. Conf. Design Automation, 2003, pp. 402-407.
[48]K. Sungchan, I. Chaeseok, and H. Soonhoi, Schedule-aware performance estimation of communication architecture for efficient design space exploration, IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 13, no. 5, pp. 539-552, May 2005.
[49]V. Reyes, W. Kruijtzer, T. Bautista, G. Alkadi, and A. Nunez, A Unified System-Level Modeling and Simulation Environment for MPSoC design: MPEG-4 Decoder Case Study, in Proc. of Design Automation and Test in Europe Conf., 2006, pp. 1-6.
[50]K. Ueda, K. Sakanushi, Y. Takeuchi, and M. Imai, Architecture-level performance estimation method based on system-level profiling, IEEE Trans. Computers and Digital Techniques, vol. 152, no. 1, pp. 12-19, Jan. 2005.
[51]S. Pasricha, N. Dutt, and M. Ben-Romdhane, Automated throughput-driven synthesis of bus-based communication architectures, in Proc. of Asia and South Pacific Design Automation Conf., 2005, pp. 495-498.
[52]K. K. Ryu and V. J. Mooney, Automated bus generation for multiprocessor SoC design, IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 23, no. 11, pp. 1531-1549, Nov. 2004.
[53]Y.-S. Cho, E.-J. Choi, and K.-R. Cho, Modeling and analysis of the system bus latency on the SoC platform, in Proc. Int. Workshop System-level interconnect prediction, 2006, pp. 67-74.
[54]S. Pandey, M. Glesner, and M. Muhlhauser, Performance Aware On-Chip Communication Synthesis and Optimization for Shared Multi-Bus Based Architecture, in Proc. Int. Symp. Integrated Circuits and Systems Design, 2005, pp. 230-235.
[55]S. Pandey, N. Utlu, and M. Glesner, Tabu Search Based On-Chip Communication Bus Synthesis for Shared Multi-Bus Based Architecture, in Proc. Int. Conf. Very Large Scale Integration, 2006, pp. 222-227.
[56]K. Lahiri, A. Raghunathan, and S. Dey, Design space exploration for optimizing on-chip communication architectures, IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 23, no. 6, pp. 952-961, June 2004.
[57]Y. Niu, J. Bian, H. Wang, K. Tong, and L. Zhu, SLCAO: an effective system level communication architectures optimization methodology for system-on- chips, in Proc. Int. Conf. ASIC, 2005, pp. 33-36.
[58]G. Lee, S. Lee, Y. Ahn, and K. Choi, Automatic Bus Matrix Synthesis based on Hardware Interface Selection for Fast Communication Design Space Exploration, in Proc. Int. Conf. Embedded Computer Systems: Architectures, Modeling and Simulation (IC-SAMOS), 2007, pp. 50-57.
[59]J. Yoo, D. Lee, S. Yoo, and K. Choi, Communication Architecture Synthesis of Cascaded Bus Matrix, in Proc. of Asia and South Pacific Design Automation Conf., 2007, pp. 171-177.
[60]S. Srinivasan, L. Li, and N. Vijaykrishnan, Simultaneous partitioning and frequency assignment for on-chip bus architectures, in Proc. of Design Automation and Test in Europe Conf., 2005, pp. 218-223.
[61]R. Barua, W. Lee, S. Amarasinghe, and A. Agarwal, Maps: a compiler-managed memory system for Raw machines, in Proc. Int. Symp. Computer Architecture, 1999, pp. 4-15.
[62]P. Grun, N. Dutt, and A. Nicolau, Access pattern based local memory customization for low power embedded systems, in Proc. of Design Automation and Test in Europe Conf., 2001, pp. 778-784.
[63]B. So, M. W. Hall, and H. E. Ziegler, Custom data layout for memory parallelism, in Proc. Int. Symp. Code Generation and Optimization, 2004, pp. 291-302.
[64]L. Cai, H. Yu, and D. Gajski, A novel memory size model for variable-mapping in system level design, in Proc. of Asia and South Pacific Design Automation Conf., 2004, pp. 813-818.
[65]T. S. Rajesh Kumar, C. P. Ravikumar, and R. Govindarajan, MODLEX: A Multi Objective Data Layout EXploration Framework for Embedded Systems-on-Chip, in Proc. of Asia and South Pacific Design Automation Conf., 2007, pp. 492-497.
[66]T. S. R. Kumar, C. P. Ravikumar, and R. Govindarajan, MAX: A Multi Objective Memory Architecture eXploration Framework for Embedded Systems-on-Chip, in Proc. Int. Conf. VLSI Design, 2007, pp. 527-533.
[67]K. Sungchan and H. Soonhoi, Efficient exploration of bus-based system-on-chip architectures, IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 14, no. 7, pp. 681-692, July 2006.
[68]S. Pasricha and N. D. Dutt, A Framework for Cosynthesis of Memory and Communication Architectures for MPSoC, IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 3, pp. 408-420, March 2007.
[69]S. Pasricha, N. Dutt, and F. J. Kurdahi, Dynamically reconfigurable on-chip communication architectures for multi use-case chip multiprocessor applications, in Proc. of Asia and South Pacific Design Automation Conf., 2009, pp. 25-30.
[70]S. Srinivasan, L. Li, M. Ruggiero, F. Angiolini, N. Vijaykrishnan, and L. Benini, Exploring architectural solutions for energy optimisations in bus-based system-on-chip, IET Computers & Digital Techniques, vol. 2, no. 5, pp. 347-354, Sept. 2008.
[71]B. H. Meyer and D. E. Thomas, Simultaneous synthesis of buses, data mapping and memory allocation for MPSoC, in Proc. Int. Conf. Hardware/Software Codesign and System Synthesis, 2007, pp. 3-8.
[72]A. H. Farrahi and M. Sarrafzadeh, System partitioning to maximize sleep time, in Proc. Int. Conf. Comput.-Aided Design, 1995, pp. 452-455.
[73]M. Farrahi, G. E. Tellez, and M. Sarrafzadeh, Memory Segmentation to Exploit Sleep Mode Operation, in Proc. Int. Conf. Design Automation, 1995, pp. 36-41.
[74]P. Ghafari, E. Mirhadi, M. Anis, A. Areibi, and M. Elmasry, A low-power partitioning methodology by maximizing sleep time and minimizing cut nets, in Proc. Int. Workshop System-on-Chip for Real-Time Applications, 2005, pp. 368-371.
[75]D. Dal and N. Mansouri, Power Optimization With Power Islands Synthesis, IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 28, no. 7, pp. 1025-1037, July 2009.
[76]L. Benini, P. Siegel, and G. De Micheli, Saving power by synthesizing gated clocks for sequential circuits, IEEE Trans. Design & Test of Computers, vol. 11, no. 4, pp. 32-41, Winter 1994.
[77]L. Changbo, X. Jinjun, and L. Yongpan, Techniques of Power-gating to Kill Sub-Threshold Leakage, in Proc. of Asia Pacific Circuits and Systems Conf., 2006, pp. 952-955.
[78]AMBA Design Kit; [Online] Available: http://www.arm.com.
[79]G. D. Micheli, Synthesis and Optimization of Digital Circuits, McGraw-Hill, New York, USA, 1994.
[80]G. Karypis and V. Kumar, Metis: A Software Package for Paritioning Unstructured Graphs, Partitioning Meshes and Computing Fill-Reducing Orderings of Sparce Matrices, University of Minnesota, Minneapolis, Technical Report MN 55455, 1998.
[81]S. Kirkpatrick, C. D. Gelatt, and M. P. Vecchi, Optimization by Simulated Annealing, Science, vol. 220, no. 4598, pp. 671-680, May 1983.
[82]E. Aarts and J. Korst, Simulated Annealing and Boltzmann Machines, Wiley & Sons, Chichester, England, 1989.
[83]H. Orsila, E. Salminen, and T. D. Hämäläinen, Best Practices for Simulated Annealing in Multiprocessor Task Distribution Problems, I-Tech Education and Publishing KG, pp. 321-342, Sept. 2008.
[84]Y.-S. Chen, L.-Y. Chiou, and H.-H. Chang, A fast and effective dynamic trace-based method for analyzing architectural performance, in Proc. of Asia and South Pacific Design Automation Conf., 2011, pp. 591-596.
[85]Synopsys Platform Architect; [Online] Available: http://www.synopsys.com/Systems/ArchitectureDesign/pages/PlatformArchitect.aspx.
[86]L.-Y. Chiou, Y.-S. Chen, and Y.-L. Jian, Energy-aware partitioning for on-chip bus architecture using a multi-objective genetic algorithm, in Proc. Int. Symp. VLSI Design Automation and Test (VLSI-DAT), 2011, pp. 1-4.
[87]K. Deb, A. Pratap, S. Agarwal, and T. Meyarivan, A fast and elitist multiobjective genetic algorithm: NSGA-II, IEEE Trans. Evolutionary Computation, vol. 6, no. 2, pp. 182-197, April 2002.
[88]R. P. Dick, D. L. Rhodes, and W. Wolf, TGFF: task graphs for free, in Proc. Int. Workshop Hardware/Software Codesign, 1998, pp. 97-101.
[89]S. Bandyopadhyay, S. Saha, U. Maulik, and K. Deb, A Simulated Annealing-Based Multiobjective Optimization Algorithm: AMOSA, IEEE Trans. Evolutionary Computation, vol. 12, no. 3, pp. 269-283, June 2008.
[90]L.-Y. Chiou, Y.-S. Chen, and C.-H. Lee, System-Level Bus-Based Communication Architecture Exploration Using a Pseudoparallel Algorithm, IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 28, no. 8, pp. 1213-1223, Aug. 2009.
[91]V. Raghunathan, M. B. Srivastava, and R. K. Gupta, A survey of techniques for energy efficient on-chip communication, in Proc. Int. Conf. Design Automation, 2003, pp. 900-905.
[92]M. Hase, K. Akie, M. Nobori, and K. Matsumoto, Development of Low-power and Real-time VC-1/H.264/MPEG-4 Video Processing Hardware, in Proc. of Asia and South Pacific Design Automation Conf., 2007, pp. 637-643.
[93]C.-C. Ju, T.-M. Liu, Y.-C. Chang, C.-M. Wang, H.-M. Lin, S. Cheng, C.-C. Chen, F. Chiu, K.-S. Lin, C.-B. Wu, S. Liang, S.-J. Wang, G. Chen, T. C. Hsiao, and C.-H. Wang, A 125Mpixels/sec full-HD MPEG-2/H.264/VC-1 video decoder for Blu-ray applications, in Proc. of Solid-State Circuits Conf., 2008, pp. 9-12.
[94]H. Nakata, K. Hosogi, M. Ehama, T. Yuasa, T. Fujihira, K. Iwata, M. Kimura, F. Izuhara, S. Mochizuki, and M. Nobori, Development of full-HD multi-standard video CODEC IP based on heterogeneous multiprocessor architecture, in Proc. of Asia and South Pacific Design Automation Conf. , 2009, pp. 528-534.
[95]T. M. Liu, T. A. Lin, S. Z. Wang, W. P. Lee, J. Y. Yang, K. C. Hou, and C. Y. Lee, A 125-µW, Fully Scalable MPEG-2 and H.264/AVC Video Decoder for Mobile Applications, IEEE J. Solid-State Circuits, vol. 42, no. 1, pp. 161-169, Jan. 2007.
[96]S. Lee and K. Cho, Circuit implementation for transform and quantization operations of H.264/MPEG-4/VC-1 video decoder, in Proc. Int. Conf. Design & Technology of Integrated Systems in Nanoscale Era, 2007, pp. 102-107.
[97]J. Zheng, W. Gao, D. Wu, and D. Xie, A novel VLSI architecture of motion compensation for multiple standards, IEEE Trans. Consumer Electronics, vol. 54, no. 2, pp. 687-694, May 2008.
連結至畢業學校之論文網頁點我開啟連結
註: 此連結為研究生畢業學校所提供,不一定有電子全文可供下載,若連結有誤,請點選上方之〝勘誤回報〞功能,我們會盡快修正,謝謝!
QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top