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研究生:周冠賢
研究生(外文):Kuan-HsienChou
論文名稱:邊界導通錯相式升壓型功因修正電路控制IC研製
論文名稱(外文):Design and Implementation of a Control IC forInterleaved BCM Boost PFCs
指導教授:梁從主
指導教授(外文):Tsorng-Juu Liang
學位類別:碩士
校院名稱:國立成功大學
系所名稱:電機工程學系碩博士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2012
畢業學年度:100
語文別:英文
論文頁數:80
中文關鍵詞:錯相式邊界導通模式主從式控制
外文關鍵詞:InterleavedBCM controlmaster-slave control
相關次數:
  • 被引用被引用:0
  • 點閱點閱:191
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  • 收藏至我的研究室書目清單書目收藏:1
本論文致力於研製一新型邊界導通錯相式升壓型功因修正電路控制IC,此控制方式不僅保有邊界導通模式的低切換損的優勢,更可大幅提升轉換器的輸出功率。本控制器採用的錯相式控制策略為電壓模式之主從式導通瞬間相移控制法。傳統的錯相控制策略有時會使電路無法保持在邊界導通模式。為了解決此問題,本文不僅提出一個新型的相移電路,並且使用了第二組的零電流偵測電路產生從電路的零切訊號,配合相移電路所產生的相移訊號,使得從電路可以保持在邊界導通模式操作。另外,當兩組儲能電感値存在偏差時,本控制IC依舊可以保持正常的操作行為。最後,本晶片採用TSMC 0.25 UM CMOS HIGH VOLTAGE MIXED SIGNAL BASED BCD 1P5M SALICIDE 2.5/5/60 V 製程實現。
In this thesis, a novel interleaved BCM boost PFC control IC is designed and implemented. This contoller not only retains the advantage of low swtiching loss of BCM control but also increases the power rating of converter. The voltage mode master-slave interleaved control with turn-on instant phase-shift is adopted in the proposed controller. Conventionally, the interleaved BCM control scheme may occasionally operate in CCM due to pertubations. To solve this problem, the thesis proposes a novel phase-shifter to generate phase-shift signal. And the second zero current detector cooperated with the phase-shift signal is utilized to make the slave converter operate under BCM. In addition, this controller can always operate in normal condition even under the mismatch of two boost inductors. Finally, this chip is fabricated with TSMC 0.25 UM CMOS HIGH VOLTAGE MIXED SIGNAL BASED BCD 1P5M SALICIDE 2.5/5/60 V process.
1. Introduction............................................1
1.1 Background.........................................1
1.2 Research motivation................................3
1.3 Organization.......................................4
2. Fundamental AC-DC power factor correction circuit and
interleaved control concepts............................5
2.1 Power factor correction circuits...................5
2.1.1 Introduction of AC-DC power factor
correction circuits.........................5
2.1.2 BCM control scheme for boost PFC............8
2.2 Basic concept of interleaved control..............10
2.2.1 Interleaved boost converter................10
2.2.2 Basic open-loop master-slave control
concepts...................................11
2.3 The operation of interleaved boost PFC converter
with BCM control..................................14
2.4 Interleaved boost PFC with conventional open-loop
BCM control scheme................................22
3. Analysis and design of the proposed controller.........26
3.1 Introduction of the proposed interleaved control..26
3.2 The operating principle of the proposed control
scheme............................................28
3.3 Introduction of the architecture..................32
3.4 Design of control function blocks.................34
3.4.1 Error amplifier............................34
3.4.2 ZCD (Zero current detector)................35
3.4.3 Reset-timer................................37
3.4.4 Master, slave PWM controller...............39
3.4.5 On-time modulator..........................41
3.4.6 Phase-shifter..............................42
3.4.7 Sequence detector..........................46
3.4.8 Slave on-time trimming.....................48
3.5 CMOS circuit design...............................48
3.5.1 Constant transconductance bias circuit.....48
3.5.2 Two-stage Op-Amp...........................51
3.5.3 Comparator.................................53
3.5.4 Edge detector..............................57
3.5.5 Buffer.....................................59
4. Layout and simulation of the proposed interleaved BCM
controller.............................................61
4.1 Layout............................................61
4.2 System simulation results.........................62
4.2.1 Waveforms of function blocks...............64
4.2.2 Interleaved system waveforms...............69
5. Conclusions and future work............................72
5.1 Conclusions.......................................72
5.2 Future works......................................72
References................................................73

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