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研究生:江杰倫
研究生(外文):Chieh-LunChiang
論文名稱:高除數除5及除7預除器之24 GHz多頻帶低相位雜訊鎖相迴路之設計
論文名稱(外文):Design of 24 GHz Multi-band Low Phase Noise Phase Locked-loop Using High-division-ratio Prescalers of Divide-by-5 and Divide-by-7
指導教授:楊慶隆楊慶隆引用關係
指導教授(外文):Chin-Lung Yang
學位類別:碩士
校院名稱:國立成功大學
系所名稱:電機工程學系碩博士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2012
畢業學年度:100
語文別:英文
論文頁數:137
中文關鍵詞:壓控振盪器鎖相迴路除5預除器除7預除器
外文關鍵詞:Voltage-controlled OscillatorPhase-locked LoopPrescaler of Divide-by-5Prescaler of Divide-by-7
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本論文提出一個可應用於400 MHz、2.4 GHz以及24 GHz之使用高除數預除器的多頻帶頻率合成器設計。這些多頻帶頻率合成器為可應用於生醫植入頻段、ISM頻段以及車用雷達頻段之重要裝置。其中,一個402 MHz的兩級環形差動式壓控振盪器,以及2.4 GHz採用抑制尾電流源記憶之互補耦合對壓控振盪器,採用高Q值元件設計以得到低相位雜訊,同時得到優異的效能指標參數(FOM)。這些設計皆以台積電提供的TSMC 0.18 μm 1P6M CMOS製程所實現。根據量測所得結果,402 MHz壓控振盪器有著從234 MHz至888 MHz的寬調頻範圍,同時也有0.34 x 0.27 mm2的小晶片實現面積;依照前一版晶片,又更進一步改進其相位雜訊以及整體效能,實現出2.4 GHz的壓控振盪器設計,其電路核心功耗為3.096 mW,相位雜訊在1-MHz偏移頻率下有著-123.26 dBc / Hz的表現能力,同時整體FOM經計算後可得到-185.96 dB之優異結果。
接著,本論文又更進一步設計使用除5預除器之多頻帶應用的24 GHz鎖相迴路,並採用壓控振盪器和除頻器中第一級預除器之連動電壓控制概念,去克服單一鎖定頻率範圍不足之問題。根據模擬結果可得知,壓控振盪器的相位雜訊在1-MHz偏移頻率下為-103.8 dBc / Hz、10-MHz偏移頻率下為-124.2 dBc / Hz,同時整體閉迴路系統之鎖定時間約450 ns,對應到鎖定電壓為0.72 V,而整體電路功率消耗約31.675 mW。此外,本論文也提出一個使用更高除數除7預除器以及改良後的低相位雜訊考畢茲壓控振盪器之24 GHz鎖相迴路設計,而上述所提到的兩個鎖相迴路規格在本論文中也有詳細比較。根據模擬結果得知,改進後的相位雜訊分別提升至1-MHz偏移頻率下為-108.38 dBc / Hz,以及10-MHz偏移頻率下為-129.50 dBc / Hz;同時,整體閉迴路系統之鎖定時間約為800 ns,對應到的鎖定電壓為0.81 V,整體電路功率消耗為40.41 mW。以上所述24 GHz鎖相迴路設計皆是使用台積電提供的TSMC TN90RF 1P9M CMOS製程。
This thesis proposed the design of a multi-band frequency synthesizer for 400 MHz, 2.4 GHz, and 24 GHz, which is carried out by high-division-ratio prescalers. These multi-band frequency synthesizers are crucial components for implantable biomedical band, industrial, scientific and medical (ISM) bands, and collision-avoidance radar bands. The 402 MHz voltage-controlled oscillator (VCO) is implemented by two-stage differential ring oscillator, and the 2.4 GHz VCO uses the architecture combining the memory reduction tail transistors to the LC-tank complementary cross-coupled pair for the high quality factor Q as well as the low phase noise to achieve overall excellent figure of merit (FOM). These designs are implemented in TSMC 0.18 μm 1P6M CMOS process. From the measurement results, the 402 MHz VCO has the wide tuning range from 234 MHz to 888 MHz, and small chip size of 0.34 x 0.27 mm2; the 2.4 GHz VCO improves the performance of 400 MHz VCO and has excellent performance in aspects of phase noise. The core power consumption is 3.096 mW, the phase noise is -123.26 dBc / Hz at 1-MHz offset frequency, and the overall FOM is excellent to achieve -185.96 dB.
Then, this thesis in advance presents a multi-band 24 GHz PLL using a prescaler of divide-by-5 with the concept of linking controlled voltage to the VCO and prescaler to overcome the insufficient frequency locking range. From the simulation results, the phase noise of VCO are -103.8 dBc / Hz at 1-MHz offset and -124.2 dBc / Hz at 10-MHz offset frequency. The locked time of PLL is approximately 450 ns while the locked voltage is 0.72 V, and the overall power consumption is 31.675 mW. In addition, a 24 GHz PLL design using a ring-oscillator-based prescaler of divide-by-7 and improved Colpitts differential VCO with low phase noise is presented, and the comparisons of above mentioned PLLs are given in this thesis. From the simulation results, the phase noise are excellent to -108.38 dBc / Hz at 1-MHz offset and -129.50 dBc / Hz at 10-MHz offset frequency respectively. The locked time is 800 ns while the locked voltage is approximately 0.81 V, and the power consumption is 40.41 mW. These designs of 24 GHz PLL are implemented in TSMC TN90RF 1P9M CMOS process.
Abstract (in Chinese) I
Abstract (in English) III
Acknowledgement V
Table of Contents VII
List of Tables XI
List of Figures XIII

Chapter 1 Introduction 1
1.1 Research Background and Motivation of the Voltage-controlled Oscillator and Phase-locked Loop 1
1.2 Introduction of Med-radio, ISM, and Collision-avoidance Radar Band 4
1.3 Introduction of Voltage-controlled Oscillator (VCO) 6
1.3.1 Ring Oscillator 7
1.3.2 LC-tank Oscillator 8
1.3.3 VCO Design Consideration Parameters 10
1.4 Introduction of Phase-locked Loop (PLL) 14
1.5 Organization of this Thesis 15

Chapter 2 A 402 MHz Small Chip Area CMOS Differential Ring VCO in Med-Radio Band for Implantable Fractal Dental Antenna System 17
2.1 Introduction of Wireless Implantable Basal Body Temperature (BBT) Measurement System 17
2.2 Architecture and Theoretical Analysis of 402 MHz VCO 19
2.3 The Simulation Results 26
2.4 Measurement Considerations and Results 29
2.4.1 Measurement Considerations 29
2.4.2 Measurement Results 30
2.5 Comparisons and Summary 33

Chapter 3 A LC-tank VCO with Memory Reduction Tail Transistors and Low Power Consumption for the 2.4 GHz IEEE 802.11b / g Application 35
3.1 Research Development and Introduction of Wireless Local Area Network (WLAN) 35
3.2 Architecture and Theoretical Analysis of 2.4 GHz LC-tank VCO with Low Phase Noise 38
3.2.1 Introduction of LC-tank VCO 38
3.2.2 Theoretical Analysis and Model Simulation 40
3.3 Simulation Results 43
3.4 Measurement Considerations and Results 47
3.4.1 Measurement Considerations 47
3.4.2 Measurement Results 48
3.5 Comparisons and Summary 52

Chapter 4 Design of the 24 GHz PLL Using Divide-by-5 Prescaler for Multi-band Applications, Including the MedRadio, ISM, and Collision-avoidance Radar Bands 55
4.1 Introduction of the 24 GHz Multi-band PLL 55
4.2 Linear Model Analysis of PLL 57
4.2.1 Analysis Equations of the Input Signal to the PLL System 58
4.2.2 Analysis Equations of LPF to the PLL System 59
4.2.3 Analysis Equations of VCO to the PLL System 59
4.3 Building Blocks of the 24 GHz Multi-band PLL 60
4.3.1 VCO 60
4.3.2 Differentially Direct Injection-locked Divide-by-5 Frequency Divider 63
4.3.3 Current Mode Logic (CML) Divide-by-2 Divider 72
4.3.4 True Single Phase Clock (TSPC) Divide-by-3 Divider 73
4.3.5 Phase and Frequency Detector (PFD) 74
4.3.6 Charge Pump (CP) 75
4.3.7 Low-pass Filter (LPF) 77
4.4 Simulation Results and Measurement Considerations 83
4.4.1 Pre-layout Simulation Results 83
4.4.2 Post-layout Simulation Results 87
4.4.3 Simulation Result Comparisons 97
4.4.4 Measurement Considerations 99
4.5 Comparisons and Summary 101
4.5.1 Literature Comparisons 101
4.5.2 Summary 101

Chapter 5 A 24 GHz PLL Design Using A High-division-ratio of Divide-by-7 ILFD for Wide Frequency Locking Range 103
5.1 Introduction of the Architecture of the 24 GHz PLL System and this Chapter 103
5.2 Comparisons of LC-tank-oscillator-based and Ring-oscillator-based ILFD 104
5.3 Building Blocks of 24 GHz PLL 107
5.4 Simulation Results and Measurement Considerations 112
5.4.1 Simulation Results 112
5.4.2 Measurement Considerations 121
5.5 Comparisons and Summary 123
5.5.1 Comparisons of PLLs Near 24 GHz 123
5.5.2 Summary 124

Chapter 6 Conclusions and Future Prospects 127
6.1 Conclusions 127
6.1.1 Design of VCO in 402 MHz MedRadio and 2.4 GHz ISM Band Applications 127
6.1.2 Design of Multi-band 24 GHz PLL Using a Divide-by-5 Prescaler 128
6.1.3 Design of 24 GHz Using a Divide-by-7 Prescaler 129
6.2 Future Prospects 130
6.2.1 Optimization of 402 MHz MedRadio Band VCO and 2.4 GHz ISM Band VCO 130
6.2.2 Optimization of Multi-band Application 24 GHz PLL Using a Divide-by-5 Prescaler 131
6.2.3 Optimization of 24 GHz PLL Using a Divide-by-7 Prescaler 131

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