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研究生:葉柏廷
研究生(外文):Bo-TingYeh
論文名稱:具死區時間自我探勘之無感測數位式切換穩壓器
論文名稱(外文):Sensorless Digital Switching Regulator with Dead-Time Self-Exploration
指導教授:蔡建泓蔡建泓引用關係
指導教授(外文):Chien-Hung Tsai
學位類別:碩士
校院名稱:國立成功大學
系所名稱:電機工程學系碩博士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2012
畢業學年度:100
語文別:中文
論文頁數:116
中文關鍵詞:直流-直流轉換器死區時間數位控制
外文關鍵詞:DC-DC converterdead-timedigital control
相關次數:
  • 被引用被引用:1
  • 點閱點閱:236
  • 評分評分:
  • 下載下載:18
  • 收藏至我的研究室書目清單書目收藏:0
本論文實作具死區時間自我探勘之無感測數位式穩壓器,使用逐漸嶄露頭角的數位電源技術,無需任何功率級或電流感測元件,實現控制器搜尋最佳化死區,能有效提升電源轉換器效率,延長電池使用壽命。同時,也提出加速搜尋最佳化死區的機制,能大幅縮短搜尋時間,快速達到目標。此外,為了避免因為死區解析度太低,而尋找到非最佳化死區時間,使用延遲電路串的方式實現,可不必需要高頻率的操作即可提高死區解析度。本論文以FPGA為實驗平台,進行量測並驗證所提出之概念,證明確實能大幅縮短搜尋時間及提昇效率。最後將已在FPGA驗證過的電路架構整合delay-line ADC以TSMC 1P6M 0.18um製程下線並量測驗證,晶片大小為1.3 mm2且量測結果也與預期相符。
This thesis presents a sensorless digital regulator with dead-time self-exploration. The dead-time controller utilizes the relationship between duty-cycle command and power-loss to find the optimized dead-time without sensing any of the power-stage signals. A exploration algorithm with delay-line circuits instead of high frequency is used to accelerate the optimized dead-time searching and provides high quantization resolution with dead-time step. This approach is well suited for digital IC implementation. The FPGA experimental results show that the proposed architecture can quickly search the optimization of the dead-time and improve efficiency. After FPGA prototyping, the proposed DC-DC converter has been implemented in TSMC 1P6M 0.18μm CMOS technology. The chip size is 1.3 mm2 and the experimental results proved the same with FPGA experimental results.
第一章 緒論 1
1.1 研究背景與動機 1
1.2 相關研究發展 3
1.3 目標與貢獻 7
1.4 論文架構簡介 8
第二章 基本降壓型數位控制切換穩壓器設計 9
2.1 系統架構 9
2.2 數位控制器設計 13
2.3 系統規格 23
2.4 ESL模型及模擬驗證平台 25
2.5 FPGA系統實作及量測結果 30
第三章 同步整流降壓型轉換器之dead-time控制 39
3.1 原理簡介 39
3.2 Dead-time於系統之操作情形 40
3.2.1 連續導通模式-電感電流大於零之情形 41
3.2.2 連續導通模式-電感電流部分低於零之情形 42
3.3 現有類比式dead-time控制技術 43
3.3.1 類比式fixed dead-time控制 43
3.3.2 Adaptive dead-time控制 44
3.3.3 Delay-locked-loop based dead-time控制 45
3.3.4 Load dependent dead-time控制 46
3.3.5 Dynamic dead-time控制 47
3.3.6 Robust dead-time控制 49
3.4 現有數位式dead-time控制技術 51
3.4.1 數位式fixed dead-time控制 51
3.4.2 Predictive dead-time控制 52
3.4.3 Perturbation-based extremum seeking dead-time控制 53
3.4.4 Sensorless dead-time控制 54
3.4.5 One-step dead-time控制 56
第四章 無感測之dead-time探勘及最佳化 59
4.1 簡介及問題 59
4.2 無感測式之dead-time快速探勘原理及設計 63
4.2.1 探勘最佳化dead-time演算法 63
4.2.2 Dead-time解析度的實現方式 69
4.3 最佳化dead-time的決定機制 71
4.4 外部情況變化中之最佳化dead-time的搜尋 73
第五章 具最佳化dead-time之降壓型數位控制切換穩壓器設計 76
5.1 系統架構與規格 76
5.2 數位控制器之運作流程 77
5.3 ESL模型及模擬驗證平台 78
5.4 FPGA系統實作及量測結果 85
5.5 比較與討論 94
第六章 晶片下線 95
6.1 系統架構與規格 95
6.2 模擬驗證 96
6.3 晶片照相圖與量測考量 99
6.4 量測設置與實驗結果 100
6.5 文獻比較表 107
第七章 結論與展望 108
7.1 總結與貢獻 108
7.2 未來工作及研究方向 108
附錄 110
參考文獻 110
投稿論文 113

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