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研究生:盧志剛
研究生(外文):Chih-KangLu
論文名稱:使用新的pHEMT絕緣製程改善ESD以及降低閘極漏電流
論文名稱(外文):New pHEMT Isolation Process for ESD Prevention and Lower Gate Leakage
指導教授:許渭州
指導教授(外文):Wei-Chou Hsu
學位類別:碩士
校院名稱:國立成功大學
系所名稱:電機工程學系專班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2012
畢業學年度:100
語文別:英文
論文頁數:53
中文關鍵詞:假型高速電子移動電晶體離子佈植濕蝕刻絕緣
外文關鍵詞:pHEMTIon ImplantationWet etchingIsolation
相關次數:
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在本論文首先被探討的是以離子佈植方式對元件做隔離絕緣,其元件尺寸為0.5X150μm2,所製作出來的pHEMT元件呈現出不錯的特性,其崩潰電壓為24.8V、最大轉導gm為260mS/mm,在高頻特性中截止頻率ft為27.8GHz、最大震盪頻率fmax為57.9GHz,但是我們在晶圓表面很容易發現到損傷,且會造成低良率,經過調查與探討發現晶圓在機台上做金屬lift-off時所造成的ESD問題,我們推斷此問題是製程與結構所造成,因此更改為濕式蝕刻做絕緣製程並實驗,結果獲得改善,但此時又出現了漏電流過高導致測試晶圓時低良率的產生。因此在本論文中將介紹新的絕緣方法來改善以上的問題。
In this thesis, the devices of investigation are fabricated by Ion Implantation on 6 inch wafer, and the gate dimension is 0.5X150μm2. It displays good performance. Breakdown voltage is 24.8V, and the maximum extrinsic transconductance (gm) is 260mS/mm. For RF performance, the cut off frequency (ft) is 27.8GHz, and the maximum oscillation frequency (fmax) is 57.9GHz. But we found lot of the surface damaged and low yield on wafer probing. For this issue, it is caused by ESD, and it is easy formation after metal lift-off. We infer this problem caused by the process and structure. So we experiment wet etching to replace Ion Implantation. But it appeared the problem of high leakage current. And the probing yield is lower. So we will introduce the new isolation technic to improve these issues in this thesis.
Abstract (Chinese) I
Abstract (English) III
Acknowledgement (Chinese) V
Contents VI
Table Caption IX
Figure Caption X
Chapter 1 Introduction 1
Chapter 2 Pseudomorphic HEMTs Structure 3
2-1 HEMT Layer Design 3
2-1-1 Cap Layer (GaAs) 3
2-1-2 Etching stop layer (AlAs) 4
2-1-3 Schottky contact layer (AlGaAs) 4
2-1-4 δ-doped layer 5
2-1-5 Undoped space layer (AlGaAs) 5
2-1-6 Undoped channel layer (InGaAs) 5
2-1-7 Undoped buffer layer 6
Chapter 3 Ion Implantation 7
3-1 Device fabrication By Ion Implantation 7
3-1-1 Source and Drain ohmic contact metal 7
3-1-2 Isolation 8
3-1-3 Gate recess and schottky contact metal 8
3-1-4 Passivation 9
3-2 Device Characteristics For Implantaion 9
3-2-1 Current-Voltage Characteristics 9
3-2-2 Threshold voltage and extrinsic
transconductance 9
3-2-3 Breakdown voltage and leakage current 10
3-2-4 RF characteristics 11
3-3 ESD Issue 12
Chapter 4 MESA Etching 13
4-1 Device Fabrication by MESA Etching 13
4-1-1 Wet etching 13
4-1-2 Source/Drain and gate metal 14
4-2 Device Characteristics For Wet Etching 14
4-2-1 Current-Voltage Characteristics 14
4-2-2 Threshold voltage and extrinsic
transconductance 15
4-2-3 Breakdown voltage 15
4-2-4 RF characteristics 15
4-3 High leakage current issue 15
Chapter 5 New Isolation Technic 17
5-1 2-In-1 Isolation Process 17
5-2 Improvement of Device Characteristics 17
5-2-1 Current-Voltage Characteristics 17
5-2-2 Threshold voltage and extrinsic
transconductance 18
5-2-3 Breakdown voltage and wafer probing 18
5-2-4 RF characteristics 17
Chapter 6 Conclusion 20
References 22
Figures 25

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